From cc37b93f38edc9351829d5d51f965c14e82e3955 Mon Sep 17 00:00:00 2001 From: StaySunny Date: Thu, 24 Jul 2025 17:16:22 +0800 Subject: [PATCH] first commit --- APP/main.c | 31 + DEV/iic | 0 DEV/iic.c | 466 ++ DEV/iic.h | 12 + .../Target_1_STM32F103C8_1.0.0.dbgconf | 36 + EventRecorderStub.scvd | 9 + Listings/example.map | 1638 +++++++ Objects/ExtDll.iex | 2 + Objects/example.axf | Bin 0 -> 39300 bytes Objects/example.build_log.htm | 117 + Objects/example.htm | 707 ++++ Objects/example.lnp | 18 + Objects/example.sct | 16 + Objects/example_Target_1.dep | 176 + Objects/gpio_stm32f10x.d | 16 + Objects/gpio_stm32f10x.o | Bin 0 -> 9872 bytes Objects/iic.d | 14 + Objects/iic.o | Bin 0 -> 17576 bytes Objects/main.d | 15 + Objects/main.o | Bin 0 -> 3536 bytes Objects/misc.d | 15 + Objects/misc.o | Bin 0 -> 6848 bytes Objects/startup_stm32f10x_md.o | Bin 0 -> 6036 bytes Objects/stm32f10x_flash.d | 15 + Objects/stm32f10x_flash.o | Bin 0 -> 20724 bytes Objects/stm32f10x_gpio.d | 15 + Objects/stm32f10x_gpio.o | Bin 0 -> 14432 bytes Objects/stm32f10x_i2c.d | 15 + Objects/stm32f10x_i2c.o | Bin 0 -> 21524 bytes Objects/stm32f10x_rcc.d | 15 + Objects/stm32f10x_rcc.o | Bin 0 -> 20148 bytes Objects/stm32f10x_spi.d | 15 + Objects/stm32f10x_spi.o | Bin 0 -> 16940 bytes Objects/stm32f10x_tim.d | 15 + Objects/stm32f10x_tim.o | Bin 0 -> 58404 bytes Objects/stm32f10x_usart.d | 15 + Objects/stm32f10x_usart.o | Bin 0 -> 20008 bytes Objects/system_stm32f10x.d | 14 + Objects/system_stm32f10x.o | Bin 0 -> 7028 bytes RTE/Device/STM32F103C8/RTE_Device.h | 1828 ++++++++ .../STM32F103C8/RTE_Device.h.base@1.1.2 | 1828 ++++++++ .../STM32F101_102_103_105_107.dbgconf | 36 + ...M32F101_102_103_105_107.dbgconf.base@1.0.0 | 36 + RTE/Device/STM32F103C8/startup_stm32f10x_md.s | 308 ++ .../startup_stm32f10x_md.s.base@1.0.1 | 308 ++ RTE/Device/STM32F103C8/stm32f10x_conf.h | 122 + .../STM32F103C8/stm32f10x_conf.h.base@3.6.0 | 122 + RTE/Device/STM32F103C8/system_stm32f10x.c | 1092 +++++ .../STM32F103C8/system_stm32f10x.c.base@1.0.1 | 1092 +++++ RTE/_Target_1/RTE_Components.h | 36 + example.uvguix.gxyos | 3746 +++++++++++++++++ example.uvoptx | 274 ++ example.uvprojx | 529 +++ 53 files changed, 14764 insertions(+) create mode 100644 APP/main.c create mode 100644 DEV/iic create mode 100644 DEV/iic.c create mode 100644 DEV/iic.h create mode 100644 DebugConfig/Target_1_STM32F103C8_1.0.0.dbgconf create mode 100644 EventRecorderStub.scvd create mode 100644 Listings/example.map create mode 100644 Objects/ExtDll.iex create mode 100644 Objects/example.axf create mode 100644 Objects/example.build_log.htm create mode 100644 Objects/example.htm create mode 100644 Objects/example.lnp create mode 100644 Objects/example.sct create mode 100644 Objects/example_Target_1.dep create mode 100644 Objects/gpio_stm32f10x.d create mode 100644 Objects/gpio_stm32f10x.o create mode 100644 Objects/iic.d create mode 100644 Objects/iic.o create mode 100644 Objects/main.d create mode 100644 Objects/main.o create mode 100644 Objects/misc.d create mode 100644 Objects/misc.o create mode 100644 Objects/startup_stm32f10x_md.o create mode 100644 Objects/stm32f10x_flash.d create mode 100644 Objects/stm32f10x_flash.o create mode 100644 Objects/stm32f10x_gpio.d create mode 100644 Objects/stm32f10x_gpio.o create mode 100644 Objects/stm32f10x_i2c.d create mode 100644 Objects/stm32f10x_i2c.o create mode 100644 Objects/stm32f10x_rcc.d create mode 100644 Objects/stm32f10x_rcc.o create mode 100644 Objects/stm32f10x_spi.d create mode 100644 Objects/stm32f10x_spi.o create mode 100644 Objects/stm32f10x_tim.d create mode 100644 Objects/stm32f10x_tim.o create mode 100644 Objects/stm32f10x_usart.d create mode 100644 Objects/stm32f10x_usart.o create mode 100644 Objects/system_stm32f10x.d create mode 100644 Objects/system_stm32f10x.o create mode 100644 RTE/Device/STM32F103C8/RTE_Device.h create mode 100644 RTE/Device/STM32F103C8/RTE_Device.h.base@1.1.2 create mode 100644 RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf create mode 100644 RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf.base@1.0.0 create mode 100644 RTE/Device/STM32F103C8/startup_stm32f10x_md.s create mode 100644 RTE/Device/STM32F103C8/startup_stm32f10x_md.s.base@1.0.1 create mode 100644 RTE/Device/STM32F103C8/stm32f10x_conf.h create mode 100644 RTE/Device/STM32F103C8/stm32f10x_conf.h.base@3.6.0 create mode 100644 RTE/Device/STM32F103C8/system_stm32f10x.c create mode 100644 RTE/Device/STM32F103C8/system_stm32f10x.c.base@1.0.1 create mode 100644 RTE/_Target_1/RTE_Components.h create mode 100644 example.uvguix.gxyos create mode 100644 example.uvoptx create mode 100644 example.uvprojx diff --git a/APP/main.c b/APP/main.c new file mode 100644 index 0000000..4945f5d --- /dev/null +++ b/APP/main.c @@ -0,0 +1,31 @@ +#include "stm32f10x.h" +#include "iic.h" + + + + +int main(){ + + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); + + GPIO_InitTypeDef gpio_init; + gpio_init.GPIO_Pin = GPIO_Pin_13; + gpio_init.GPIO_Speed = GPIO_Speed_50MHz; + gpio_init.GPIO_Mode = GPIO_Mode_Out_PP; + + GPIO_Init(GPIOC,&gpio_init); + + GPIO_ResetBits(GPIOC, GPIO_Pin_13); + + + + + + test(); + + while(1); + + + return 0; +} \ No newline at end of file diff --git a/DEV/iic b/DEV/iic new file mode 100644 index 0000000..e69de29 diff --git a/DEV/iic.c b/DEV/iic.c new file mode 100644 index 0000000..377fc63 --- /dev/null +++ b/DEV/iic.c @@ -0,0 +1,466 @@ +#include "iic.h" +#include "stm32f10x.h" + + +#include + + + + + +const uint8_t Font6x8[][6] = { + // SPACE (0x20) + {0x00,0x00,0x00,0x00,0x00,0x00}, // ' ' + {0x00,0x00,0x5F,0x00,0x00,0x00}, // '!' + {0x00,0x07,0x00,0x07,0x00,0x00}, // '"' + {0x14,0x7F,0x14,0x7F,0x14,0x00}, // '#' + {0x24,0x2A,0x7F,0x2A,0x12,0x00}, // '$' + {0x23,0x13,0x08,0x64,0x62,0x00}, // '%' + {0x36,0x49,0x55,0x22,0x50,0x00}, // '&' + {0x00,0x05,0x03,0x00,0x00,0x00}, // ''' + {0x00,0x1C,0x22,0x41,0x00,0x00}, // '(' + {0x00,0x41,0x22,0x1C,0x00,0x00}, // ')' + {0x14,0x08,0x3E,0x08,0x14,0x00}, // '*' + {0x08,0x08,0x3E,0x08,0x08,0x00}, // '+' + {0x00,0x50,0x30,0x00,0x00,0x00}, // ',' + {0x08,0x08,0x08,0x08,0x08,0x00}, // '-' + {0x00,0x60,0x60,0x00,0x00,0x00}, // '.' + {0x20,0x10,0x08,0x04,0x02,0x00}, // '/' + + {0x3E,0x51,0x49,0x45,0x3E,0x00}, // '0' (0x30) + {0x00,0x42,0x7F,0x40,0x00,0x00}, // '1' + {0x42,0x61,0x51,0x49,0x46,0x00}, // '2' + {0x21,0x41,0x45,0x4B,0x31,0x00}, // '3' + {0x18,0x14,0x12,0x7F,0x10,0x00}, // '4' + {0x27,0x45,0x45,0x45,0x39,0x00}, // '5' + {0x3C,0x4A,0x49,0x49,0x30,0x00}, // '6' + {0x01,0x71,0x09,0x05,0x03,0x00}, // '7' + {0x36,0x49,0x49,0x49,0x36,0x00}, // '8' + {0x06,0x49,0x49,0x29,0x1E,0x00}, // '9' + + {0x00,0x36,0x36,0x00,0x00,0x00}, // ':' (0x3A) + {0x00,0x56,0x36,0x00,0x00,0x00}, // ';' + {0x08,0x14,0x22,0x41,0x00,0x00}, // '<' + {0x14,0x14,0x14,0x14,0x14,0x00}, // '=' + {0x00,0x41,0x22,0x14,0x08,0x00}, // '>' + {0x02,0x01,0x51,0x09,0x06,0x00}, // '?' + + {0x32,0x49,0x79,0x41,0x3E,0x00}, // '@' (0x40) + {0x7E,0x11,0x11,0x11,0x7E,0x00}, // 'A' + {0x7F,0x49,0x49,0x49,0x36,0x00}, // 'B' + {0x3E,0x41,0x41,0x41,0x22,0x00}, // 'C' + {0x7F,0x41,0x41,0x22,0x1C,0x00}, // 'D' + {0x7F,0x49,0x49,0x49,0x41,0x00}, // 'E' + {0x7F,0x09,0x09,0x09,0x01,0x00}, // 'F' + {0x3E,0x41,0x49,0x49,0x7A,0x00}, // 'G' + {0x7F,0x08,0x08,0x08,0x7F,0x00}, // 'H' + {0x00,0x41,0x7F,0x41,0x00,0x00}, // 'I' + {0x20,0x40,0x41,0x3F,0x01,0x00}, // 'J' + {0x7F,0x08,0x14,0x22,0x41,0x00}, // 'K' + {0x7F,0x40,0x40,0x40,0x40,0x00}, // 'L' + {0x7F,0x02,0x0C,0x02,0x7F,0x00}, // 'M' + {0x7F,0x04,0x08,0x10,0x7F,0x00}, // 'N' + {0x3E,0x41,0x41,0x41,0x3E,0x00}, // 'O' + + {0x7F,0x09,0x09,0x09,0x06,0x00}, // 'P' (0x50) + {0x3E,0x41,0x51,0x21,0x5E,0x00}, // 'Q' + {0x7F,0x09,0x19,0x29,0x46,0x00}, // 'R' + {0x46,0x49,0x49,0x49,0x31,0x00}, // 'S' + {0x01,0x01,0x7F,0x01,0x01,0x00}, // 'T' + {0x3F,0x40,0x40,0x40,0x3F,0x00}, // 'U' + {0x1F,0x20,0x40,0x20,0x1F,0x00}, // 'V' + {0x3F,0x40,0x38,0x40,0x3F,0x00}, // 'W' + {0x63,0x14,0x08,0x14,0x63,0x00}, // 'X' + {0x07,0x08,0x70,0x08,0x07,0x00}, // 'Y' + {0x61,0x51,0x49,0x45,0x43,0x00}, // 'Z' + + {0x00,0x7F,0x41,0x41,0x00,0x00}, // '[' + {0x02,0x04,0x08,0x10,0x20,0x00}, // '\' + {0x00,0x41,0x41,0x7F,0x00,0x00}, // ']' + {0x04,0x02,0x01,0x02,0x04,0x00}, // '^' + {0x80,0x80,0x80,0x80,0x80,0x00}, // '_' + {0x00,0x03,0x05,0x00,0x00,0x00}, // '`' + + {0x20,0x54,0x54,0x54,0x78,0x00}, // 'a' (0x61) + {0x7F,0x48,0x44,0x44,0x38,0x00}, // 'b' + {0x38,0x44,0x44,0x44,0x20,0x00}, // 'c' + {0x38,0x44,0x44,0x48,0x7F,0x00}, // 'd' + {0x38,0x54,0x54,0x54,0x18,0x00}, // 'e' + {0x08,0x7E,0x09,0x01,0x02,0x00}, // 'f' + {0x0C,0x52,0x52,0x52,0x3E,0x00}, // 'g' + {0x7F,0x08,0x04,0x04,0x78,0x00}, // 'h' + {0x00,0x44,0x7D,0x40,0x00,0x00}, // 'i' + {0x20,0x40,0x44,0x3D,0x00,0x00}, // 'j' + {0x7F,0x10,0x28,0x44,0x00,0x00}, // 'k' + {0x00,0x41,0x7F,0x40,0x00,0x00}, // 'l' + {0x7C,0x04,0x18,0x04,0x78,0x00}, // 'm' + {0x7C,0x08,0x04,0x04,0x78,0x00}, // 'n' + {0x38,0x44,0x44,0x44,0x38,0x00}, // 'o' + + {0x7C,0x14,0x14,0x14,0x08,0x00}, // 'p' (0x70) + {0x08,0x14,0x14,0x18,0x7C,0x00}, // 'q' + {0x7C,0x08,0x04,0x04,0x08,0x00}, // 'r' + {0x48,0x54,0x54,0x54,0x20,0x00}, // 's' + {0x04,0x3F,0x44,0x40,0x20,0x00}, // 't' + {0x3C,0x40,0x40,0x20,0x7C,0x00}, // 'u' + {0x1C,0x20,0x40,0x20,0x1C,0x00}, // 'v' + {0x3C,0x40,0x30,0x40,0x3C,0x00}, // 'w' + {0x44,0x28,0x10,0x28,0x44,0x00}, // 'x' + {0x0C,0x50,0x50,0x50,0x3C,0x00}, // 'y' + {0x44,0x64,0x54,0x4C,0x44,0x00}, // 'z' + + {0x08,0x36,0x41,0x00,0x00,0x00}, // '{' + {0x00,0x00,0x7F,0x00,0x00,0x00}, // '|' + {0x00,0x41,0x36,0x08,0x00,0x00}, // '}' + {0x02,0x01,0x02,0x04,0x02,0x00}, // '~' +}; + +#define OLED_WIDTH 128 +#define OLED_HEIGHT 64 + +// OLED 显存，1bit 表示一个像素（黑白屏） +// 128 * 64 / 8 = 1024 字节 +uint8_t OLED_GRAM[8][128]; // 8页，每页8行，共64行 + +#define SDA_PIN GPIO_Pin_8 +#define SCL_PIN GPIO_Pin_9 +#define I2C_PORT GPIOB + +#define SDA_HIGH() GPIO_SetBits(I2C_PORT, SDA_PIN) +#define SDA_LOW() GPIO_ResetBits(I2C_PORT, SDA_PIN) +#define SCL_HIGH() GPIO_SetBits(I2C_PORT, SCL_PIN) +#define SCL_LOW() GPIO_ResetBits(I2C_PORT, SCL_PIN) + +#define READ_SDA() GPIO_ReadInputDataBit(I2C_PORT, SDA_PIN) + + +void delay(){ + __NOP(); + +} + +void delay_us_simple(uint32_t us) +{ + uint32_t i; + while(us--) + { + for(i = 0; i < 8; i++); // 简单调整这个数字以匹配频率 + } +} + +void delay_ms_simple(uint32_t ms) +{ + while(ms--) + { + delay_us_simple(1000); // 1000 微秒 = 1 毫秒 + } +} + + + +void IIC_GPIO_Init(void) +{ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = SDA_PIN | SCL_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; // ???? + GPIO_Init(I2C_PORT, &GPIO_InitStructure); + + SDA_HIGH(); + SCL_HIGH(); +} + + +void IIC_Delay(void) +{ + //delay(1); // 5us 延时，100kHz I2C +} + +void IIC_Start(void) +{ + SDA_HIGH(); + SCL_HIGH(); + IIC_Delay(); + SDA_LOW(); + IIC_Delay(); + SCL_LOW(); + IIC_Delay(); +} + +void IIC_Stop(void) +{ + SDA_LOW(); + SCL_HIGH(); + IIC_Delay(); + SDA_HIGH(); + IIC_Delay(); +} + +void IIC_Send_Byte(uint8_t data) +{ + for (int i = 0; i < 8; i++) { + if (data & 0x80) + SDA_HIGH(); + else + SDA_LOW(); + data <<= 1; + + IIC_Delay(); + SCL_HIGH(); + IIC_Delay(); + SCL_LOW(); + IIC_Delay(); + } +} + +uint8_t IIC_Read_Byte(uint8_t ack) +{ + uint8_t data = 0; + + SDA_HIGH(); // 释放 SDA + + for (int i = 0; i < 8; i++) { + data <<= 1; + SCL_HIGH(); + IIC_Delay(); + if (READ_SDA()) data |= 1; + SCL_LOW(); + IIC_Delay(); + } + + // 发送 ACK 或 NACK + if (ack) + SDA_LOW(); + else + SDA_HIGH(); + + IIC_Delay(); + SCL_HIGH(); + IIC_Delay(); + SCL_LOW(); + SDA_HIGH(); // 释放 SDA + + return data; +} + +uint8_t IIC_Wait_Ack(void) +{ + uint8_t timeout = 0; + + SDA_HIGH(); // 释放 SDA + IIC_Delay(); + SCL_HIGH(); + IIC_Delay(); + + while (READ_SDA()) { + timeout++; + if (timeout > 250) { + IIC_Stop(); + return 1; // 失败 + } + } + + SCL_LOW(); + return 0; // 成功 +} + +void IIC_Ack(void) +{ + SDA_LOW(); + IIC_Delay(); + SCL_HIGH(); + IIC_Delay(); + SCL_LOW(); + SDA_HIGH(); +} + +void IIC_NAck(void) +{ + SDA_HIGH(); + IIC_Delay(); + SCL_HIGH(); + IIC_Delay(); + SCL_LOW(); +} + + +void OLED_WriteCommand(uint8_t cmd) +{ + IIC_Start(); + IIC_Send_Byte(0x78); // I2C 地址 + IIC_Wait_Ack(); + IIC_Send_Byte(0x00); // 写命令 + IIC_Wait_Ack(); + IIC_Send_Byte(cmd); + IIC_Wait_Ack(); + IIC_Stop(); +} + +void OLED_WriteData(uint8_t data) +{ + IIC_Start(); + IIC_Send_Byte(0x78); + IIC_Wait_Ack(); + IIC_Send_Byte(0x40); // 写数据 + IIC_Wait_Ack(); + IIC_Send_Byte(data); + IIC_Wait_Ack(); + IIC_Stop(); +} + + + +void OLED_Fill(uint8_t data) +{ + for(uint8_t page = 0; page < 8; page++) + { + OLED_WriteCommand(0xB0 + page); // 页地址 + OLED_WriteCommand(0x00); // 列低地址 + OLED_WriteCommand(0x10); // 列高地址 + + for(uint8_t col = 0; col < 128; col++) + { + OLED_WriteData(data); + } + } +} + +void OLED_Init(void) +{ + delay_ms_simple(100); // 等待 OLED 上电稳定 + + OLED_WriteCommand(0xAE); // 关闭显示 + + OLED_WriteCommand(0x20); // 设置内存地址模式 + OLED_WriteCommand(0x10); // 00,水平地址模式; 01,垂直地址模式; 10,页地址模式（默认） + + OLED_WriteCommand(0xB0); // 设置页起始地址（0~7） + + OLED_WriteCommand(0xC8); // COM输出扫描方向：从 COM[N-1] 到 COM0 + + OLED_WriteCommand(0x00); // 设置低列起始地址 + OLED_WriteCommand(0x10); // 设置高列起始地址 + + OLED_WriteCommand(0x40); // 设置起始行地址（0~63） + + OLED_WriteCommand(0x81); // 对比度设置 + OLED_WriteCommand(0xFF); // 对比度值（0x00~0xFF） + + OLED_WriteCommand(0xA1); // 段重映射：正常（A0），反转（A1） + + OLED_WriteCommand(0xA6); // 显示正常（A6），反相显示（A7） + + OLED_WriteCommand(0xA8); // 多路复用率 + OLED_WriteCommand(0x3F); // 1/64 duty（0x3F） + + OLED_WriteCommand(0xA4); // 全局显示开启，输出跟随 RAM 内容 + + OLED_WriteCommand(0xD3); // 设置显示偏移 + OLED_WriteCommand(0x00); // 无偏移 + + OLED_WriteCommand(0xD5); // 设置显示时钟分频比/振荡器频率 + OLED_WriteCommand(0x80); // 推荐值 + + OLED_WriteCommand(0xD9); // 设置预充电周期 + OLED_WriteCommand(0xF1); // 推荐值 + + OLED_WriteCommand(0xDA); // 设置 COM 引脚配置 + OLED_WriteCommand(0x12); + + OLED_WriteCommand(0xDB); // 设置 VCOMH 电压倍率 + OLED_WriteCommand(0x40); // 推荐值 + + OLED_WriteCommand(0x8D); // 使能电荷泵 + OLED_WriteCommand(0x14); // 开启 + + OLED_WriteCommand(0xAF); // 开启显示 + + OLED_Fill(0xFF); // 清屏 +} + +void OLED_DrawPixel(uint8_t x, uint8_t y, uint8_t color) { + if (x >= OLED_WIDTH || y >= OLED_HEIGHT) return; + + if (color) + OLED_GRAM[y / 8][x] |= (1 << (y % 8)); + else + OLED_GRAM[y / 8][x] &= ~(1 << (y % 8)); +} + + + +void OLED_Refresh(void) { + for (uint8_t page = 0; page < 8; page++) { + OLED_WriteCommand(0xB0 + page); // 设置页地址 + OLED_WriteCommand(0x00); // 设置低列地址 + OLED_WriteCommand(0x10); // 设置高列地址 + + for (uint8_t col = 0; col < OLED_WIDTH; col++) { + OLED_WriteData(OLED_GRAM[page][col]); + } + } +} +void OLED_ShowChar(uint8_t x, uint8_t y, char chr) { + if (x > OLED_WIDTH - 6 || y > 7) return; + + uint8_t c = chr - 32; // ASCII偏移 + for (uint8_t i = 0; i < 6; i++) { + OLED_GRAM[y][x + i] = Font6x8[c][i]; + } +} + + + + +void lcd_show_all_ascii_lowercase() { + uint16_t x = 0, y = 0; + char ch = 'a'; + + for (int row = 0; row < 10; row++) { + for (int col = 0; col < 16; col++) { + OLED_ShowChar(x, y, ch); // 白色 + x += 8; + ch++; + if (ch > 'z') ch = 'a'; // 循环 a-z + } + x = 0; + y += 16; + } +} + +void test(){ + + + + + IIC_GPIO_Init(); + + OLED_Init(); + + lcd_show_all_ascii_lowercase(); + + OLED_Refresh(); + + while(1){ + + //OLED_Fill(0xFF); // 清屏 + //delay_ms_simple(1000); + + //OLED_Fill(0x00); + //delay_ms_simple(1000); + + + + } + + +} + + + + + + + diff --git a/DEV/iic.h b/DEV/iic.h new file mode 100644 index 0000000..1887432 --- /dev/null +++ b/DEV/iic.h @@ -0,0 +1,12 @@ +#ifndef _IIC_H_ +#define _IIC_H_ + + +void test(); + + + + + + +#endif \ No newline at end of file diff --git a/DebugConfig/Target_1_STM32F103C8_1.0.0.dbgconf b/DebugConfig/Target_1_STM32F103C8_1.0.0.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/DebugConfig/Target_1_STM32F103C8_1.0.0.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/EventRecorderStub.scvd b/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/Listings/example.map b/Listings/example.map new file mode 100644 index 0000000..9c9b181 --- /dev/null +++ b/Listings/example.map @@ -0,0 +1,1638 @@ +Component: Arm Compiler for Embedded 6.23 Tool: armlink [5f102400] + +============================================================================== + +Section Cross References + + main.o(.text.main) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + main.o(.text.main) refers to stm32f10x_gpio.o(.text.GPIO_Init) for GPIO_Init + main.o(.text.main) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + main.o(.text.main) refers to iic.o(.text.test) for test + main.o(.ARM.exidx.text.main) refers to main.o(.text.main) for [Anonymous Symbol] + iic.o(.ARM.exidx.text.delay) refers to iic.o(.text.delay) for [Anonymous Symbol] + iic.o(.ARM.exidx.text.delay_us_simple) refers to iic.o(.text.delay_us_simple) for [Anonymous Symbol] + iic.o(.text.delay_ms_simple) refers to iic.o(.text.delay_us_simple) for delay_us_simple + iic.o(.ARM.exidx.text.delay_ms_simple) refers to iic.o(.text.delay_ms_simple) for [Anonymous Symbol] + iic.o(.text.IIC_GPIO_Init) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + iic.o(.text.IIC_GPIO_Init) refers to stm32f10x_gpio.o(.text.GPIO_Init) for GPIO_Init + iic.o(.text.IIC_GPIO_Init) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.ARM.exidx.text.IIC_GPIO_Init) refers to iic.o(.text.IIC_GPIO_Init) for [Anonymous Symbol] + iic.o(.ARM.exidx.text.IIC_Delay) refers to iic.o(.text.IIC_Delay) for [Anonymous Symbol] + iic.o(.text.IIC_Start) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.text.IIC_Start) refers to iic.o(.text.IIC_Delay) for IIC_Delay + iic.o(.text.IIC_Start) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + iic.o(.ARM.exidx.text.IIC_Start) refers to iic.o(.text.IIC_Start) for [Anonymous Symbol] + iic.o(.text.IIC_Stop) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + iic.o(.text.IIC_Stop) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.text.IIC_Stop) refers to iic.o(.text.IIC_Delay) for IIC_Delay + iic.o(.ARM.exidx.text.IIC_Stop) refers to iic.o(.text.IIC_Stop) for [Anonymous Symbol] + iic.o(.text.IIC_Send_Byte) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.text.IIC_Send_Byte) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + iic.o(.text.IIC_Send_Byte) refers to iic.o(.text.IIC_Delay) for IIC_Delay + iic.o(.ARM.exidx.text.IIC_Send_Byte) refers to iic.o(.text.IIC_Send_Byte) for [Anonymous Symbol] + iic.o(.text.IIC_Read_Byte) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.text.IIC_Read_Byte) refers to iic.o(.text.IIC_Delay) for IIC_Delay + iic.o(.text.IIC_Read_Byte) refers to stm32f10x_gpio.o(.text.GPIO_ReadInputDataBit) for GPIO_ReadInputDataBit + iic.o(.text.IIC_Read_Byte) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + iic.o(.ARM.exidx.text.IIC_Read_Byte) refers to iic.o(.text.IIC_Read_Byte) for [Anonymous Symbol] + iic.o(.text.IIC_Wait_Ack) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.text.IIC_Wait_Ack) refers to iic.o(.text.IIC_Delay) for IIC_Delay + iic.o(.text.IIC_Wait_Ack) refers to stm32f10x_gpio.o(.text.GPIO_ReadInputDataBit) for GPIO_ReadInputDataBit + iic.o(.text.IIC_Wait_Ack) refers to iic.o(.text.IIC_Stop) for IIC_Stop + iic.o(.text.IIC_Wait_Ack) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + iic.o(.ARM.exidx.text.IIC_Wait_Ack) refers to iic.o(.text.IIC_Wait_Ack) for [Anonymous Symbol] + iic.o(.text.IIC_Ack) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + iic.o(.text.IIC_Ack) refers to iic.o(.text.IIC_Delay) for IIC_Delay + iic.o(.text.IIC_Ack) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.ARM.exidx.text.IIC_Ack) refers to iic.o(.text.IIC_Ack) for [Anonymous Symbol] + iic.o(.text.IIC_NAck) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for GPIO_SetBits + iic.o(.text.IIC_NAck) refers to iic.o(.text.IIC_Delay) for IIC_Delay + iic.o(.text.IIC_NAck) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for GPIO_ResetBits + iic.o(.ARM.exidx.text.IIC_NAck) refers to iic.o(.text.IIC_NAck) for [Anonymous Symbol] + iic.o(.text.OLED_WriteCommand) refers to iic.o(.text.IIC_Start) for IIC_Start + iic.o(.text.OLED_WriteCommand) refers to iic.o(.text.IIC_Send_Byte) for IIC_Send_Byte + iic.o(.text.OLED_WriteCommand) refers to iic.o(.text.IIC_Wait_Ack) for IIC_Wait_Ack + iic.o(.text.OLED_WriteCommand) refers to iic.o(.text.IIC_Stop) for IIC_Stop + iic.o(.ARM.exidx.text.OLED_WriteCommand) refers to iic.o(.text.OLED_WriteCommand) for [Anonymous Symbol] + iic.o(.text.OLED_WriteData) refers to iic.o(.text.IIC_Start) for IIC_Start + iic.o(.text.OLED_WriteData) refers to iic.o(.text.IIC_Send_Byte) for IIC_Send_Byte + iic.o(.text.OLED_WriteData) refers to iic.o(.text.IIC_Wait_Ack) for IIC_Wait_Ack + iic.o(.text.OLED_WriteData) refers to iic.o(.text.IIC_Stop) for IIC_Stop + iic.o(.ARM.exidx.text.OLED_WriteData) refers to iic.o(.text.OLED_WriteData) for [Anonymous Symbol] + iic.o(.text.OLED_Fill) refers to iic.o(.text.OLED_WriteCommand) for OLED_WriteCommand + iic.o(.text.OLED_Fill) refers to iic.o(.text.OLED_WriteData) for OLED_WriteData + iic.o(.ARM.exidx.text.OLED_Fill) refers to iic.o(.text.OLED_Fill) for [Anonymous Symbol] + iic.o(.text.OLED_Init) refers to iic.o(.text.delay_ms_simple) for delay_ms_simple + iic.o(.text.OLED_Init) refers to iic.o(.text.OLED_WriteCommand) for OLED_WriteCommand + iic.o(.text.OLED_Init) refers to iic.o(.text.OLED_Fill) for OLED_Fill + iic.o(.ARM.exidx.text.OLED_Init) refers to iic.o(.text.OLED_Init) for [Anonymous Symbol] + iic.o(.text.OLED_DrawPixel) refers to iic.o(.bss.OLED_GRAM) for OLED_GRAM + iic.o(.ARM.exidx.text.OLED_DrawPixel) refers to iic.o(.text.OLED_DrawPixel) for [Anonymous Symbol] + iic.o(.text.OLED_Refresh) refers to iic.o(.text.OLED_WriteCommand) for OLED_WriteCommand + iic.o(.text.OLED_Refresh) refers to iic.o(.bss.OLED_GRAM) for OLED_GRAM + iic.o(.text.OLED_Refresh) refers to iic.o(.text.OLED_WriteData) for OLED_WriteData + iic.o(.ARM.exidx.text.OLED_Refresh) refers to iic.o(.text.OLED_Refresh) for [Anonymous Symbol] + iic.o(.text.OLED_ShowChar) refers to iic.o(.rodata.Font6x8) for Font6x8 + iic.o(.text.OLED_ShowChar) refers to iic.o(.bss.OLED_GRAM) for OLED_GRAM + iic.o(.ARM.exidx.text.OLED_ShowChar) refers to iic.o(.text.OLED_ShowChar) for [Anonymous Symbol] + iic.o(.text.lcd_show_all_ascii_lowercase) refers to iic.o(.text.OLED_ShowChar) for OLED_ShowChar + iic.o(.ARM.exidx.text.lcd_show_all_ascii_lowercase) refers to iic.o(.text.lcd_show_all_ascii_lowercase) for [Anonymous Symbol] + iic.o(.text.test) refers to iic.o(.text.IIC_GPIO_Init) for IIC_GPIO_Init + iic.o(.text.test) refers to iic.o(.text.OLED_Init) for OLED_Init + iic.o(.text.test) refers to iic.o(.text.lcd_show_all_ascii_lowercase) for lcd_show_all_ascii_lowercase + iic.o(.text.test) refers to iic.o(.text.OLED_Refresh) for OLED_Refresh + iic.o(.ARM.exidx.text.test) refers to iic.o(.text.test) for [Anonymous Symbol] + misc.o(.ARM.exidx.text.NVIC_PriorityGroupConfig) refers to misc.o(.text.NVIC_PriorityGroupConfig) for [Anonymous Symbol] + misc.o(.ARM.exidx.text.NVIC_Init) refers to misc.o(.text.NVIC_Init) for [Anonymous Symbol] + misc.o(.ARM.exidx.text.NVIC_SetVectorTable) refers to misc.o(.text.NVIC_SetVectorTable) for [Anonymous Symbol] + misc.o(.ARM.exidx.text.NVIC_SystemLPConfig) refers to misc.o(.text.NVIC_SystemLPConfig) for [Anonymous Symbol] + misc.o(.ARM.exidx.text.SysTick_CLKSourceConfig) refers to misc.o(.text.SysTick_CLKSourceConfig) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_SetLatency) refers to stm32f10x_flash.o(.text.FLASH_SetLatency) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_HalfCycleAccessCmd) refers to stm32f10x_flash.o(.text.FLASH_HalfCycleAccessCmd) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_PrefetchBufferCmd) refers to stm32f10x_flash.o(.text.FLASH_PrefetchBufferCmd) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_Unlock) refers to stm32f10x_flash.o(.text.FLASH_Unlock) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_UnlockBank1) refers to stm32f10x_flash.o(.text.FLASH_UnlockBank1) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_Lock) refers to stm32f10x_flash.o(.text.FLASH_Lock) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_LockBank1) refers to stm32f10x_flash.o(.text.FLASH_LockBank1) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_ErasePage) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_ErasePage) refers to stm32f10x_flash.o(.text.FLASH_ErasePage) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32f10x_flash.o(.text.FLASH_GetBank1Status) for FLASH_GetBank1Status + stm32f10x_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_EraseAllPages) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_EraseAllPages) refers to stm32f10x_flash.o(.text.FLASH_EraseAllPages) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_EraseAllBank1Pages) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastBank1Operation) for FLASH_WaitForLastBank1Operation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_EraseAllBank1Pages) refers to stm32f10x_flash.o(.text.FLASH_EraseAllBank1Pages) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_WaitForLastBank1Operation) refers to stm32f10x_flash.o(.text.FLASH_GetBank1Status) for FLASH_GetBank1Status + stm32f10x_flash.o(.ARM.exidx.text.FLASH_WaitForLastBank1Operation) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastBank1Operation) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(.text.FLASH_GetReadOutProtectionStatus) for FLASH_GetReadOutProtectionStatus + stm32f10x_flash.o(.text.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(.text.FLASH_EraseOptionBytes) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetReadOutProtectionStatus) refers to stm32f10x_flash.o(.text.FLASH_GetReadOutProtectionStatus) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_ProgramWord) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_ProgramWord) refers to stm32f10x_flash.o(.text.FLASH_ProgramWord) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_ProgramHalfWord) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_ProgramHalfWord) refers to stm32f10x_flash.o(.text.FLASH_ProgramHalfWord) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_ProgramOptionByteData) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_ProgramOptionByteData) refers to stm32f10x_flash.o(.text.FLASH_ProgramOptionByteData) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_EnableWriteProtection) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_EnableWriteProtection) refers to stm32f10x_flash.o(.text.FLASH_EnableWriteProtection) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_ReadOutProtection) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_ReadOutProtection) refers to stm32f10x_flash.o(.text.FLASH_ReadOutProtection) for [Anonymous Symbol] + stm32f10x_flash.o(.text.FLASH_UserOptionByteConfig) refers to stm32f10x_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(.ARM.exidx.text.FLASH_UserOptionByteConfig) refers to stm32f10x_flash.o(.text.FLASH_UserOptionByteConfig) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetUserOptionByte) refers to stm32f10x_flash.o(.text.FLASH_GetUserOptionByte) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetWriteProtectionOptionByte) refers to stm32f10x_flash.o(.text.FLASH_GetWriteProtectionOptionByte) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetPrefetchBufferStatus) refers to stm32f10x_flash.o(.text.FLASH_GetPrefetchBufferStatus) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_ITConfig) refers to stm32f10x_flash.o(.text.FLASH_ITConfig) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetFlagStatus) refers to stm32f10x_flash.o(.text.FLASH_GetFlagStatus) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_ClearFlag) refers to stm32f10x_flash.o(.text.FLASH_ClearFlag) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetStatus) refers to stm32f10x_flash.o(.text.FLASH_GetStatus) for [Anonymous Symbol] + stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetBank1Status) refers to stm32f10x_flash.o(.text.FLASH_GetBank1Status) for [Anonymous Symbol] + stm32f10x_gpio.o(.text.GPIO_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_DeInit) refers to stm32f10x_gpio.o(.text.GPIO_DeInit) for [Anonymous Symbol] + stm32f10x_gpio.o(.text.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_AFIODeInit) refers to stm32f10x_gpio.o(.text.GPIO_AFIODeInit) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_Init) refers to stm32f10x_gpio.o(.text.GPIO_Init) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_StructInit) refers to stm32f10x_gpio.o(.text.GPIO_StructInit) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadInputDataBit) refers to stm32f10x_gpio.o(.text.GPIO_ReadInputDataBit) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadInputData) refers to stm32f10x_gpio.o(.text.GPIO_ReadInputData) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadOutputDataBit) refers to stm32f10x_gpio.o(.text.GPIO_ReadOutputDataBit) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadOutputData) refers to stm32f10x_gpio.o(.text.GPIO_ReadOutputData) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_SetBits) refers to stm32f10x_gpio.o(.text.GPIO_SetBits) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ResetBits) refers to stm32f10x_gpio.o(.text.GPIO_ResetBits) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_WriteBit) refers to stm32f10x_gpio.o(.text.GPIO_WriteBit) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_Write) refers to stm32f10x_gpio.o(.text.GPIO_Write) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_PinLockConfig) refers to stm32f10x_gpio.o(.text.GPIO_PinLockConfig) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_EventOutputConfig) refers to stm32f10x_gpio.o(.text.GPIO_EventOutputConfig) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_EventOutputCmd) refers to stm32f10x_gpio.o(.text.GPIO_EventOutputCmd) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_PinRemapConfig) refers to stm32f10x_gpio.o(.text.GPIO_PinRemapConfig) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_EXTILineConfig) refers to stm32f10x_gpio.o(.text.GPIO_EXTILineConfig) for [Anonymous Symbol] + stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ETH_MediaInterfaceConfig) refers to stm32f10x_gpio.o(.text.GPIO_ETH_MediaInterfaceConfig) for [Anonymous Symbol] + stm32f10x_i2c.o(.text.I2C_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_i2c.o(.ARM.exidx.text.I2C_DeInit) refers to stm32f10x_i2c.o(.text.I2C_DeInit) for [Anonymous Symbol] + stm32f10x_i2c.o(.text.I2C_Init) refers to stm32f10x_rcc.o(.text.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_i2c.o(.ARM.exidx.text.I2C_Init) refers to stm32f10x_i2c.o(.text.I2C_Init) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_StructInit) refers to stm32f10x_i2c.o(.text.I2C_StructInit) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_Cmd) refers to stm32f10x_i2c.o(.text.I2C_Cmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_DMACmd) refers to stm32f10x_i2c.o(.text.I2C_DMACmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_DMALastTransferCmd) refers to stm32f10x_i2c.o(.text.I2C_DMALastTransferCmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_GenerateSTART) refers to stm32f10x_i2c.o(.text.I2C_GenerateSTART) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_GenerateSTOP) refers to stm32f10x_i2c.o(.text.I2C_GenerateSTOP) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_AcknowledgeConfig) refers to stm32f10x_i2c.o(.text.I2C_AcknowledgeConfig) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_OwnAddress2Config) refers to stm32f10x_i2c.o(.text.I2C_OwnAddress2Config) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_DualAddressCmd) refers to stm32f10x_i2c.o(.text.I2C_DualAddressCmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_GeneralCallCmd) refers to stm32f10x_i2c.o(.text.I2C_GeneralCallCmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_ITConfig) refers to stm32f10x_i2c.o(.text.I2C_ITConfig) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_SendData) refers to stm32f10x_i2c.o(.text.I2C_SendData) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_ReceiveData) refers to stm32f10x_i2c.o(.text.I2C_ReceiveData) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_Send7bitAddress) refers to stm32f10x_i2c.o(.text.I2C_Send7bitAddress) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_ReadRegister) refers to stm32f10x_i2c.o(.text.I2C_ReadRegister) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_SoftwareResetCmd) refers to stm32f10x_i2c.o(.text.I2C_SoftwareResetCmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_NACKPositionConfig) refers to stm32f10x_i2c.o(.text.I2C_NACKPositionConfig) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_SMBusAlertConfig) refers to stm32f10x_i2c.o(.text.I2C_SMBusAlertConfig) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_TransmitPEC) refers to stm32f10x_i2c.o(.text.I2C_TransmitPEC) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_PECPositionConfig) refers to stm32f10x_i2c.o(.text.I2C_PECPositionConfig) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_CalculatePEC) refers to stm32f10x_i2c.o(.text.I2C_CalculatePEC) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetPEC) refers to stm32f10x_i2c.o(.text.I2C_GetPEC) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_ARPCmd) refers to stm32f10x_i2c.o(.text.I2C_ARPCmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_StretchClockCmd) refers to stm32f10x_i2c.o(.text.I2C_StretchClockCmd) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_FastModeDutyCycleConfig) refers to stm32f10x_i2c.o(.text.I2C_FastModeDutyCycleConfig) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_CheckEvent) refers to stm32f10x_i2c.o(.text.I2C_CheckEvent) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetLastEvent) refers to stm32f10x_i2c.o(.text.I2C_GetLastEvent) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetFlagStatus) refers to stm32f10x_i2c.o(.text.I2C_GetFlagStatus) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_ClearFlag) refers to stm32f10x_i2c.o(.text.I2C_ClearFlag) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetITStatus) refers to stm32f10x_i2c.o(.text.I2C_GetITStatus) for [Anonymous Symbol] + stm32f10x_i2c.o(.ARM.exidx.text.I2C_ClearITPendingBit) refers to stm32f10x_i2c.o(.text.I2C_ClearITPendingBit) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_DeInit) refers to stm32f10x_rcc.o(.text.RCC_DeInit) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_HSEConfig) refers to stm32f10x_rcc.o(.text.RCC_HSEConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.text.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(.text.RCC_GetFlagStatus) for RCC_GetFlagStatus + stm32f10x_rcc.o(.ARM.exidx.text.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(.text.RCC_WaitForHSEStartUp) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetFlagStatus) refers to stm32f10x_rcc.o(.text.RCC_GetFlagStatus) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_AdjustHSICalibrationValue) refers to stm32f10x_rcc.o(.text.RCC_AdjustHSICalibrationValue) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_HSICmd) refers to stm32f10x_rcc.o(.text.RCC_HSICmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_PLLConfig) refers to stm32f10x_rcc.o(.text.RCC_PLLConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_PLLCmd) refers to stm32f10x_rcc.o(.text.RCC_PLLCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_SYSCLKConfig) refers to stm32f10x_rcc.o(.text.RCC_SYSCLKConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetSYSCLKSource) refers to stm32f10x_rcc.o(.text.RCC_GetSYSCLKSource) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_HCLKConfig) refers to stm32f10x_rcc.o(.text.RCC_HCLKConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_PCLK1Config) refers to stm32f10x_rcc.o(.text.RCC_PCLK1Config) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_PCLK2Config) refers to stm32f10x_rcc.o(.text.RCC_PCLK2Config) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_ITConfig) refers to stm32f10x_rcc.o(.text.RCC_ITConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_USBCLKConfig) refers to stm32f10x_rcc.o(.text.RCC_USBCLKConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_ADCCLKConfig) refers to stm32f10x_rcc.o(.text.RCC_ADCCLKConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_LSEConfig) refers to stm32f10x_rcc.o(.text.RCC_LSEConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_LSICmd) refers to stm32f10x_rcc.o(.text.RCC_LSICmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_RTCCLKConfig) refers to stm32f10x_rcc.o(.text.RCC_RTCCLKConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_RTCCLKCmd) refers to stm32f10x_rcc.o(.text.RCC_RTCCLKCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.text.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.rodata.APBAHBPrescTable) for APBAHBPrescTable + stm32f10x_rcc.o(.text.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.rodata.ADCPrescTable) for ADCPrescTable + stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.text.RCC_GetClocksFreq) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_AHBPeriphClockCmd) refers to stm32f10x_rcc.o(.text.RCC_AHBPeriphClockCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB2PeriphClockCmd) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphClockCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB1PeriphClockCmd) refers to stm32f10x_rcc.o(.text.RCC_APB1PeriphClockCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB2PeriphResetCmd) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphResetCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB1PeriphResetCmd) refers to stm32f10x_rcc.o(.text.RCC_APB1PeriphResetCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_BackupResetCmd) refers to stm32f10x_rcc.o(.text.RCC_BackupResetCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_ClockSecuritySystemCmd) refers to stm32f10x_rcc.o(.text.RCC_ClockSecuritySystemCmd) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_MCOConfig) refers to stm32f10x_rcc.o(.text.RCC_MCOConfig) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_ClearFlag) refers to stm32f10x_rcc.o(.text.RCC_ClearFlag) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetITStatus) refers to stm32f10x_rcc.o(.text.RCC_GetITStatus) for [Anonymous Symbol] + stm32f10x_rcc.o(.ARM.exidx.text.RCC_ClearITPendingBit) refers to stm32f10x_rcc.o(.text.RCC_ClearITPendingBit) for [Anonymous Symbol] + stm32f10x_spi.o(.text.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(.text.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_DeInit) refers to stm32f10x_spi.o(.text.SPI_I2S_DeInit) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_Init) refers to stm32f10x_spi.o(.text.SPI_Init) for [Anonymous Symbol] + stm32f10x_spi.o(.text.I2S_Init) refers to stm32f10x_rcc.o(.text.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_spi.o(.ARM.exidx.text.I2S_Init) refers to stm32f10x_spi.o(.text.I2S_Init) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_StructInit) refers to stm32f10x_spi.o(.text.SPI_StructInit) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.I2S_StructInit) refers to stm32f10x_spi.o(.text.I2S_StructInit) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_Cmd) refers to stm32f10x_spi.o(.text.SPI_Cmd) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.I2S_Cmd) refers to stm32f10x_spi.o(.text.I2S_Cmd) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ITConfig) refers to stm32f10x_spi.o(.text.SPI_I2S_ITConfig) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_DMACmd) refers to stm32f10x_spi.o(.text.SPI_I2S_DMACmd) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_SendData) refers to stm32f10x_spi.o(.text.SPI_I2S_SendData) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ReceiveData) refers to stm32f10x_spi.o(.text.SPI_I2S_ReceiveData) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_NSSInternalSoftwareConfig) refers to stm32f10x_spi.o(.text.SPI_NSSInternalSoftwareConfig) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_SSOutputCmd) refers to stm32f10x_spi.o(.text.SPI_SSOutputCmd) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_DataSizeConfig) refers to stm32f10x_spi.o(.text.SPI_DataSizeConfig) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_TransmitCRC) refers to stm32f10x_spi.o(.text.SPI_TransmitCRC) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_CalculateCRC) refers to stm32f10x_spi.o(.text.SPI_CalculateCRC) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_GetCRC) refers to stm32f10x_spi.o(.text.SPI_GetCRC) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_GetCRCPolynomial) refers to stm32f10x_spi.o(.text.SPI_GetCRCPolynomial) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_BiDirectionalLineConfig) refers to stm32f10x_spi.o(.text.SPI_BiDirectionalLineConfig) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_GetFlagStatus) refers to stm32f10x_spi.o(.text.SPI_I2S_GetFlagStatus) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ClearFlag) refers to stm32f10x_spi.o(.text.SPI_I2S_ClearFlag) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_GetITStatus) refers to stm32f10x_spi.o(.text.SPI_I2S_GetITStatus) for [Anonymous Symbol] + stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ClearITPendingBit) refers to stm32f10x_spi.o(.text.SPI_I2S_ClearITPendingBit) for [Anonymous Symbol] + stm32f10x_tim.o(.text.TIM_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_tim.o(.text.TIM_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_tim.o(.ARM.exidx.text.TIM_DeInit) refers to stm32f10x_tim.o(.text.TIM_DeInit) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_TimeBaseInit) refers to stm32f10x_tim.o(.text.TIM_TimeBaseInit) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1Init) refers to stm32f10x_tim.o(.text.TIM_OC1Init) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2Init) refers to stm32f10x_tim.o(.text.TIM_OC2Init) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3Init) refers to stm32f10x_tim.o(.text.TIM_OC3Init) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4Init) refers to stm32f10x_tim.o(.text.TIM_OC4Init) for [Anonymous Symbol] + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TI1_Config) for TI1_Config + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TI2_Config) for TI2_Config + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TI3_Config) for TI3_Config + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TI4_Config) for TI4_Config + stm32f10x_tim.o(.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler + stm32f10x_tim.o(.ARM.exidx.text.TIM_ICInit) refers to stm32f10x_tim.o(.text.TIM_ICInit) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TI1_Config) refers to stm32f10x_tim.o(.text.TI1_Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC1Prescaler) refers to stm32f10x_tim.o(.text.TIM_SetIC1Prescaler) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TI2_Config) refers to stm32f10x_tim.o(.text.TI2_Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC2Prescaler) refers to stm32f10x_tim.o(.text.TIM_SetIC2Prescaler) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TI3_Config) refers to stm32f10x_tim.o(.text.TI3_Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC3Prescaler) refers to stm32f10x_tim.o(.text.TIM_SetIC3Prescaler) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TI4_Config) refers to stm32f10x_tim.o(.text.TI4_Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC4Prescaler) refers to stm32f10x_tim.o(.text.TIM_SetIC4Prescaler) for [Anonymous Symbol] + stm32f10x_tim.o(.text.TIM_PWMIConfig) refers to stm32f10x_tim.o(.text.TI1_Config) for TI1_Config + stm32f10x_tim.o(.text.TIM_PWMIConfig) refers to stm32f10x_tim.o(.text.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(.text.TIM_PWMIConfig) refers to stm32f10x_tim.o(.text.TI2_Config) for TI2_Config + stm32f10x_tim.o(.text.TIM_PWMIConfig) refers to stm32f10x_tim.o(.text.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(.ARM.exidx.text.TIM_PWMIConfig) refers to stm32f10x_tim.o(.text.TIM_PWMIConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_BDTRConfig) refers to stm32f10x_tim.o(.text.TIM_BDTRConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_TimeBaseStructInit) refers to stm32f10x_tim.o(.text.TIM_TimeBaseStructInit) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OCStructInit) refers to stm32f10x_tim.o(.text.TIM_OCStructInit) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ICStructInit) refers to stm32f10x_tim.o(.text.TIM_ICStructInit) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_BDTRStructInit) refers to stm32f10x_tim.o(.text.TIM_BDTRStructInit) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_Cmd) refers to stm32f10x_tim.o(.text.TIM_Cmd) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_CtrlPWMOutputs) refers to stm32f10x_tim.o(.text.TIM_CtrlPWMOutputs) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ITConfig) refers to stm32f10x_tim.o(.text.TIM_ITConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GenerateEvent) refers to stm32f10x_tim.o(.text.TIM_GenerateEvent) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_DMAConfig) refers to stm32f10x_tim.o(.text.TIM_DMAConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_DMACmd) refers to stm32f10x_tim.o(.text.TIM_DMACmd) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_InternalClockConfig) refers to stm32f10x_tim.o(.text.TIM_InternalClockConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.text.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(.text.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + stm32f10x_tim.o(.ARM.exidx.text.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(.text.TIM_ITRxExternalClockConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectInputTrigger) refers to stm32f10x_tim.o(.text.TIM_SelectInputTrigger) for [Anonymous Symbol] + stm32f10x_tim.o(.text.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(.text.TI2_Config) for TI2_Config + stm32f10x_tim.o(.text.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(.text.TI1_Config) for TI1_Config + stm32f10x_tim.o(.text.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(.text.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + stm32f10x_tim.o(.ARM.exidx.text.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(.text.TIM_TIxExternalClockConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.text.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(.text.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(.ARM.exidx.text.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(.text.TIM_ETRClockMode1Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ETRConfig) refers to stm32f10x_tim.o(.text.TIM_ETRConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.text.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(.text.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(.ARM.exidx.text.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(.text.TIM_ETRClockMode2Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_PrescalerConfig) refers to stm32f10x_tim.o(.text.TIM_PrescalerConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_CounterModeConfig) refers to stm32f10x_tim.o(.text.TIM_CounterModeConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_EncoderInterfaceConfig) refers to stm32f10x_tim.o(.text.TIM_EncoderInterfaceConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC1Config) refers to stm32f10x_tim.o(.text.TIM_ForcedOC1Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC2Config) refers to stm32f10x_tim.o(.text.TIM_ForcedOC2Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC3Config) refers to stm32f10x_tim.o(.text.TIM_ForcedOC3Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC4Config) refers to stm32f10x_tim.o(.text.TIM_ForcedOC4Config) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ARRPreloadConfig) refers to stm32f10x_tim.o(.text.TIM_ARRPreloadConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectCOM) refers to stm32f10x_tim.o(.text.TIM_SelectCOM) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectCCDMA) refers to stm32f10x_tim.o(.text.TIM_SelectCCDMA) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_CCPreloadControl) refers to stm32f10x_tim.o(.text.TIM_CCPreloadControl) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1PreloadConfig) refers to stm32f10x_tim.o(.text.TIM_OC1PreloadConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2PreloadConfig) refers to stm32f10x_tim.o(.text.TIM_OC2PreloadConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3PreloadConfig) refers to stm32f10x_tim.o(.text.TIM_OC3PreloadConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4PreloadConfig) refers to stm32f10x_tim.o(.text.TIM_OC4PreloadConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1FastConfig) refers to stm32f10x_tim.o(.text.TIM_OC1FastConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2FastConfig) refers to stm32f10x_tim.o(.text.TIM_OC2FastConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3FastConfig) refers to stm32f10x_tim.o(.text.TIM_OC3FastConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4FastConfig) refers to stm32f10x_tim.o(.text.TIM_OC4FastConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC1Ref) refers to stm32f10x_tim.o(.text.TIM_ClearOC1Ref) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC2Ref) refers to stm32f10x_tim.o(.text.TIM_ClearOC2Ref) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC3Ref) refers to stm32f10x_tim.o(.text.TIM_ClearOC3Ref) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC4Ref) refers to stm32f10x_tim.o(.text.TIM_ClearOC4Ref) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1PolarityConfig) refers to stm32f10x_tim.o(.text.TIM_OC1PolarityConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1NPolarityConfig) refers to stm32f10x_tim.o(.text.TIM_OC1NPolarityConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2PolarityConfig) refers to stm32f10x_tim.o(.text.TIM_OC2PolarityConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2NPolarityConfig) refers to stm32f10x_tim.o(.text.TIM_OC2NPolarityConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3PolarityConfig) refers to stm32f10x_tim.o(.text.TIM_OC3PolarityConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3NPolarityConfig) refers to stm32f10x_tim.o(.text.TIM_OC3NPolarityConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4PolarityConfig) refers to stm32f10x_tim.o(.text.TIM_OC4PolarityConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_CCxCmd) refers to stm32f10x_tim.o(.text.TIM_CCxCmd) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_CCxNCmd) refers to stm32f10x_tim.o(.text.TIM_CCxNCmd) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectOCxM) refers to stm32f10x_tim.o(.text.TIM_SelectOCxM) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_UpdateDisableConfig) refers to stm32f10x_tim.o(.text.TIM_UpdateDisableConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_UpdateRequestConfig) refers to stm32f10x_tim.o(.text.TIM_UpdateRequestConfig) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectHallSensor) refers to stm32f10x_tim.o(.text.TIM_SelectHallSensor) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectOnePulseMode) refers to stm32f10x_tim.o(.text.TIM_SelectOnePulseMode) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectOutputTrigger) refers to stm32f10x_tim.o(.text.TIM_SelectOutputTrigger) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectSlaveMode) refers to stm32f10x_tim.o(.text.TIM_SelectSlaveMode) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectMasterSlaveMode) refers to stm32f10x_tim.o(.text.TIM_SelectMasterSlaveMode) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCounter) refers to stm32f10x_tim.o(.text.TIM_SetCounter) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetAutoreload) refers to stm32f10x_tim.o(.text.TIM_SetAutoreload) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare1) refers to stm32f10x_tim.o(.text.TIM_SetCompare1) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare2) refers to stm32f10x_tim.o(.text.TIM_SetCompare2) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare3) refers to stm32f10x_tim.o(.text.TIM_SetCompare3) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare4) refers to stm32f10x_tim.o(.text.TIM_SetCompare4) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_SetClockDivision) refers to stm32f10x_tim.o(.text.TIM_SetClockDivision) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture1) refers to stm32f10x_tim.o(.text.TIM_GetCapture1) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture2) refers to stm32f10x_tim.o(.text.TIM_GetCapture2) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture3) refers to stm32f10x_tim.o(.text.TIM_GetCapture3) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture4) refers to stm32f10x_tim.o(.text.TIM_GetCapture4) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCounter) refers to stm32f10x_tim.o(.text.TIM_GetCounter) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetPrescaler) refers to stm32f10x_tim.o(.text.TIM_GetPrescaler) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetFlagStatus) refers to stm32f10x_tim.o(.text.TIM_GetFlagStatus) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearFlag) refers to stm32f10x_tim.o(.text.TIM_ClearFlag) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_GetITStatus) refers to stm32f10x_tim.o(.text.TIM_GetITStatus) for [Anonymous Symbol] + stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearITPendingBit) refers to stm32f10x_tim.o(.text.TIM_ClearITPendingBit) for [Anonymous Symbol] + stm32f10x_usart.o(.text.USART_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_usart.o(.text.USART_DeInit) refers to stm32f10x_rcc.o(.text.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_usart.o(.ARM.exidx.text.USART_DeInit) refers to stm32f10x_usart.o(.text.USART_DeInit) for [Anonymous Symbol] + stm32f10x_usart.o(.text.USART_Init) refers to stm32f10x_rcc.o(.text.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_usart.o(.ARM.exidx.text.USART_Init) refers to stm32f10x_usart.o(.text.USART_Init) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_StructInit) refers to stm32f10x_usart.o(.text.USART_StructInit) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_ClockInit) refers to stm32f10x_usart.o(.text.USART_ClockInit) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_ClockStructInit) refers to stm32f10x_usart.o(.text.USART_ClockStructInit) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_Cmd) refers to stm32f10x_usart.o(.text.USART_Cmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_ITConfig) refers to stm32f10x_usart.o(.text.USART_ITConfig) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_DMACmd) refers to stm32f10x_usart.o(.text.USART_DMACmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_SetAddress) refers to stm32f10x_usart.o(.text.USART_SetAddress) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_WakeUpConfig) refers to stm32f10x_usart.o(.text.USART_WakeUpConfig) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_ReceiverWakeUpCmd) refers to stm32f10x_usart.o(.text.USART_ReceiverWakeUpCmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_LINBreakDetectLengthConfig) refers to stm32f10x_usart.o(.text.USART_LINBreakDetectLengthConfig) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_LINCmd) refers to stm32f10x_usart.o(.text.USART_LINCmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_SendData) refers to stm32f10x_usart.o(.text.USART_SendData) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_ReceiveData) refers to stm32f10x_usart.o(.text.USART_ReceiveData) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_SendBreak) refers to stm32f10x_usart.o(.text.USART_SendBreak) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_SetGuardTime) refers to stm32f10x_usart.o(.text.USART_SetGuardTime) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_SetPrescaler) refers to stm32f10x_usart.o(.text.USART_SetPrescaler) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_SmartCardCmd) refers to stm32f10x_usart.o(.text.USART_SmartCardCmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_SmartCardNACKCmd) refers to stm32f10x_usart.o(.text.USART_SmartCardNACKCmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_HalfDuplexCmd) refers to stm32f10x_usart.o(.text.USART_HalfDuplexCmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_OverSampling8Cmd) refers to stm32f10x_usart.o(.text.USART_OverSampling8Cmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_OneBitMethodCmd) refers to stm32f10x_usart.o(.text.USART_OneBitMethodCmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_IrDAConfig) refers to stm32f10x_usart.o(.text.USART_IrDAConfig) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_IrDACmd) refers to stm32f10x_usart.o(.text.USART_IrDACmd) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_GetFlagStatus) refers to stm32f10x_usart.o(.text.USART_GetFlagStatus) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_ClearFlag) refers to stm32f10x_usart.o(.text.USART_ClearFlag) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_GetITStatus) refers to stm32f10x_usart.o(.text.USART_GetITStatus) for [Anonymous Symbol] + stm32f10x_usart.o(.ARM.exidx.text.USART_ClearITPendingBit) refers to stm32f10x_usart.o(.text.USART_ClearITPendingBit) for [Anonymous Symbol] + gpio_stm32f10x.o(.ARM.exidx.text.GPIO_PortClock) refers to gpio_stm32f10x.o(.text.GPIO_PortClock) for [Anonymous Symbol] + gpio_stm32f10x.o(.ARM.exidx.text.GPIO_GetPortClockState) refers to gpio_stm32f10x.o(.text.GPIO_GetPortClockState) for [Anonymous Symbol] + gpio_stm32f10x.o(.text.GPIO_PinConfigure) refers to gpio_stm32f10x.o(.text.GPIO_GetPortClockState) for GPIO_GetPortClockState + gpio_stm32f10x.o(.text.GPIO_PinConfigure) refers to gpio_stm32f10x.o(.text.GPIO_PortClock) for GPIO_PortClock + gpio_stm32f10x.o(.ARM.exidx.text.GPIO_PinConfigure) refers to gpio_stm32f10x.o(.text.GPIO_PinConfigure) for [Anonymous Symbol] + gpio_stm32f10x.o(.ARM.exidx.text.GPIO_AFConfigure) refers to gpio_stm32f10x.o(.text.GPIO_AFConfigure) for [Anonymous Symbol] + startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler + startup_stm32f10x_md.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(.text.SystemInit) for SystemInit + startup_stm32f10x_md.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(HEAP) for Heap_Mem + startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(STACK) for Stack_Mem + system_stm32f10x.o(.text.SystemInit) refers to system_stm32f10x.o(.text.SetSysClock) for SetSysClock + system_stm32f10x.o(.ARM.exidx.text.SystemInit) refers to system_stm32f10x.o(.text.SystemInit) for [Anonymous Symbol] + system_stm32f10x.o(.text.SetSysClock) refers to system_stm32f10x.o(.text.SetSysClockTo72) for SetSysClockTo72 + system_stm32f10x.o(.ARM.exidx.text.SetSysClock) refers to system_stm32f10x.o(.text.SetSysClock) for [Anonymous Symbol] + system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data.SystemCoreClock) for SystemCoreClock + system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.rodata.AHBPrescTable) for AHBPrescTable + system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.text.SystemCoreClockUpdate) for [Anonymous Symbol] + system_stm32f10x.o(.ARM.exidx.text.SetSysClockTo72) refers to system_stm32f10x.o(.text.SetSysClockTo72) for [Anonymous Symbol] + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f10x_md.o(.text) for __user_initial_stackheap + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000034) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000006) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000010) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_relocate_pie_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000035) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000027) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$0000001A) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000028) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000029) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.text), (0 bytes). + Removing main.o(.ARM.exidx.text.main), (8 bytes). + Removing main.o(.ARM.use_no_argv), (4 bytes). + Removing iic.o(.text), (0 bytes). + Removing iic.o(.text.delay), (4 bytes). + Removing iic.o(.ARM.exidx.text.delay), (8 bytes). + Removing iic.o(.ARM.exidx.text.delay_us_simple), (8 bytes). + Removing iic.o(.ARM.exidx.text.delay_ms_simple), (8 bytes). + Removing iic.o(.ARM.exidx.text.IIC_GPIO_Init), (8 bytes). + Removing iic.o(.ARM.exidx.text.IIC_Delay), (8 bytes). + Removing iic.o(.ARM.exidx.text.IIC_Start), (8 bytes). + Removing iic.o(.ARM.exidx.text.IIC_Stop), (8 bytes). + Removing iic.o(.ARM.exidx.text.IIC_Send_Byte), (8 bytes). + Removing iic.o(.text.IIC_Read_Byte), (234 bytes). + Removing iic.o(.ARM.exidx.text.IIC_Read_Byte), (8 bytes). + Removing iic.o(.ARM.exidx.text.IIC_Wait_Ack), (8 bytes). + Removing iic.o(.text.IIC_Ack), (64 bytes). + Removing iic.o(.ARM.exidx.text.IIC_Ack), (8 bytes). + Removing iic.o(.text.IIC_NAck), (54 bytes). + Removing iic.o(.ARM.exidx.text.IIC_NAck), (8 bytes). + Removing iic.o(.ARM.exidx.text.OLED_WriteCommand), (8 bytes). + Removing iic.o(.ARM.exidx.text.OLED_WriteData), (8 bytes). + Removing iic.o(.ARM.exidx.text.OLED_Fill), (8 bytes). + Removing iic.o(.ARM.exidx.text.OLED_Init), (8 bytes). + Removing iic.o(.text.OLED_DrawPixel), (136 bytes). + Removing iic.o(.ARM.exidx.text.OLED_DrawPixel), (8 bytes). + Removing iic.o(.ARM.exidx.text.OLED_Refresh), (8 bytes). + Removing iic.o(.ARM.exidx.text.OLED_ShowChar), (8 bytes). + Removing iic.o(.ARM.exidx.text.lcd_show_all_ascii_lowercase), (8 bytes). + Removing iic.o(.ARM.exidx.text.test), (8 bytes). + Removing misc.o(.text), (0 bytes). + Removing misc.o(.text.NVIC_PriorityGroupConfig), (28 bytes). + Removing misc.o(.ARM.exidx.text.NVIC_PriorityGroupConfig), (8 bytes). + Removing misc.o(.text.NVIC_Init), (166 bytes). + Removing misc.o(.ARM.exidx.text.NVIC_Init), (8 bytes). + Removing misc.o(.text.NVIC_SetVectorTable), (36 bytes). + Removing misc.o(.ARM.exidx.text.NVIC_SetVectorTable), (8 bytes). + Removing misc.o(.text.NVIC_SystemLPConfig), (62 bytes). + Removing misc.o(.ARM.exidx.text.NVIC_SystemLPConfig), (8 bytes). + Removing misc.o(.text.SysTick_CLKSourceConfig), (52 bytes). + Removing misc.o(.ARM.exidx.text.SysTick_CLKSourceConfig), (8 bytes). + Removing stm32f10x_flash.o(.text), (0 bytes). + Removing stm32f10x_flash.o(.text.FLASH_SetLatency), (44 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_SetLatency), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_HalfCycleAccessCmd), (32 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_HalfCycleAccessCmd), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_PrefetchBufferCmd), (32 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_PrefetchBufferCmd), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_Unlock), (30 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_Unlock), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_UnlockBank1), (30 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_UnlockBank1), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_Lock), (18 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_Lock), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_LockBank1), (18 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_LockBank1), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_ErasePage), (106 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_ErasePage), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_WaitForLastOperation), (94 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_EraseAllPages), (92 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_EraseAllPages), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_EraseAllBank1Pages), (92 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_EraseAllBank1Pages), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_WaitForLastBank1Operation), (94 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_WaitForLastBank1Operation), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_EraseOptionBytes), (254 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_EraseOptionBytes), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_GetReadOutProtectionStatus), (50 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetReadOutProtectionStatus), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_ProgramWord), (160 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_ProgramWord), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_ProgramHalfWord), (98 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_ProgramHalfWord), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_ProgramOptionByteData), (142 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_ProgramOptionByteData), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_EnableWriteProtection), (360 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_EnableWriteProtection), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_ReadOutProtection), (258 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_ReadOutProtection), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_UserOptionByteConfig), (170 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_UserOptionByteConfig), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_GetUserOptionByte), (14 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetUserOptionByte), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_GetWriteProtectionOptionByte), (12 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetWriteProtectionOptionByte), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_GetPrefetchBufferStatus), (50 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetPrefetchBufferStatus), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_ITConfig), (56 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_ITConfig), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_GetFlagStatus), (96 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetFlagStatus), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_ClearFlag), (20 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_ClearFlag), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_GetStatus), (104 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetStatus), (8 bytes). + Removing stm32f10x_flash.o(.text.FLASH_GetBank1Status), (104 bytes). + Removing stm32f10x_flash.o(.ARM.exidx.text.FLASH_GetBank1Status), (8 bytes). + Removing stm32f10x_gpio.o(.text), (0 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_DeInit), (276 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_DeInit), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_AFIODeInit), (26 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_AFIODeInit), (8 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_Init), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_StructInit), (28 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_StructInit), (8 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadInputDataBit), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_ReadInputData), (14 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadInputData), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_ReadOutputDataBit), (52 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadOutputDataBit), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_ReadOutputData), (14 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ReadOutputData), (8 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_SetBits), (8 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ResetBits), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_WriteBit), (44 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_WriteBit), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_Write), (20 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_Write), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_PinLockConfig), (60 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_PinLockConfig), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_EventOutputConfig), (64 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_EventOutputConfig), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_EventOutputCmd), (22 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_EventOutputCmd), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_PinRemapConfig), (250 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_PinRemapConfig), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_EXTILineConfig), (84 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_EXTILineConfig), (8 bytes). + Removing stm32f10x_gpio.o(.text.GPIO_ETH_MediaInterfaceConfig), (18 bytes). + Removing stm32f10x_gpio.o(.ARM.exidx.text.GPIO_ETH_MediaInterfaceConfig), (8 bytes). + Removing stm32f10x_i2c.o(.text), (0 bytes). + Removing stm32f10x_i2c.o(.text.I2C_DeInit), (70 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_DeInit), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_Init), (426 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_Init), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_StructInit), (46 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_StructInit), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_Cmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_Cmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_DMACmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_DMACmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_DMALastTransferCmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_DMALastTransferCmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_GenerateSTART), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_GenerateSTART), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_GenerateSTOP), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_GenerateSTOP), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_AcknowledgeConfig), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_AcknowledgeConfig), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_OwnAddress2Config), (64 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_OwnAddress2Config), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_DualAddressCmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_DualAddressCmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_GeneralCallCmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_GeneralCallCmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_ITConfig), (52 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_ITConfig), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_SendData), (20 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_SendData), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_ReceiveData), (14 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_ReceiveData), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_Send7bitAddress), (60 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_Send7bitAddress), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_ReadRegister), (34 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_ReadRegister), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_SoftwareResetCmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_SoftwareResetCmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_NACKPositionConfig), (48 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_NACKPositionConfig), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_SMBusAlertConfig), (48 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_SMBusAlertConfig), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_TransmitPEC), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_TransmitPEC), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_PECPositionConfig), (48 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_PECPositionConfig), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_CalculatePEC), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_CalculatePEC), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_GetPEC), (14 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetPEC), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_ARPCmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_ARPCmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_StretchClockCmd), (44 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_StretchClockCmd), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_FastModeDutyCycleConfig), (48 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_FastModeDutyCycleConfig), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_CheckEvent), (84 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_CheckEvent), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_GetLastEvent), (48 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetLastEvent), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_GetFlagStatus), (98 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetFlagStatus), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_ClearFlag), (30 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_ClearFlag), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_GetITStatus), (80 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_GetITStatus), (8 bytes). + Removing stm32f10x_i2c.o(.text.I2C_ClearITPendingBit), (30 bytes). + Removing stm32f10x_i2c.o(.ARM.exidx.text.I2C_ClearITPendingBit), (8 bytes). + Removing stm32f10x_rcc.o(.text), (0 bytes). + Removing stm32f10x_rcc.o(.text.RCC_DeInit), (82 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_DeInit), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_HSEConfig), (92 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_HSEConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_WaitForHSEStartUp), (108 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_WaitForHSEStartUp), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_GetFlagStatus), (130 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetFlagStatus), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_AdjustHSICalibrationValue), (50 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_AdjustHSICalibrationValue), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_HSICmd), (22 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_HSICmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_PLLConfig), (50 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_PLLConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_PLLCmd), (22 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_PLLCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_SYSCLKConfig), (44 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_SYSCLKConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_GetSYSCLKSource), (16 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetSYSCLKSource), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_HCLKConfig), (44 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_HCLKConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_PCLK1Config), (44 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_PCLK1Config), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_PCLK2Config), (46 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_PCLK2Config), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_ITConfig), (62 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_ITConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_USBCLKConfig), (18 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_USBCLKConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_ADCCLKConfig), (44 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_ADCCLKConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_LSEConfig), (76 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_LSEConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_LSICmd), (24 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_LSICmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_RTCCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_RTCCLKConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_RTCCLKCmd), (24 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_RTCCLKCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_GetClocksFreq), (370 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetClocksFreq), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_AHBPeriphClockCmd), (56 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_AHBPeriphClockCmd), (8 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB2PeriphClockCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_APB1PeriphClockCmd), (56 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB1PeriphClockCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_APB2PeriphResetCmd), (56 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB2PeriphResetCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_APB1PeriphResetCmd), (56 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_APB1PeriphResetCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_BackupResetCmd), (24 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_BackupResetCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_ClockSecuritySystemCmd), (22 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_ClockSecuritySystemCmd), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_MCOConfig), (24 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_MCOConfig), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_ClearFlag), (18 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_ClearFlag), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_GetITStatus), (56 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_GetITStatus), (8 bytes). + Removing stm32f10x_rcc.o(.text.RCC_ClearITPendingBit), (24 bytes). + Removing stm32f10x_rcc.o(.ARM.exidx.text.RCC_ClearITPendingBit), (8 bytes). + Removing stm32f10x_rcc.o(.rodata.APBAHBPrescTable), (16 bytes). + Removing stm32f10x_rcc.o(.rodata.ADCPrescTable), (4 bytes). + Removing stm32f10x_spi.o(.text), (0 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_DeInit), (128 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_DeInit), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_Init), (104 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_Init), (8 bytes). + Removing stm32f10x_spi.o(.text.I2S_Init), (372 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.I2S_Init), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_StructInit), (48 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_StructInit), (8 bytes). + Removing stm32f10x_spi.o(.text.I2S_StructInit), (36 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.I2S_StructInit), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_Cmd), (44 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_Cmd), (8 bytes). + Removing stm32f10x_spi.o(.text.I2S_Cmd), (44 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.I2S_Cmd), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_ITConfig), (84 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ITConfig), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_DMACmd), (52 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_DMACmd), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_SendData), (20 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_SendData), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_ReceiveData), (12 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ReceiveData), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_NSSInternalSoftwareConfig), (50 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_NSSInternalSoftwareConfig), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_SSOutputCmd), (44 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_SSOutputCmd), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_DataSizeConfig), (34 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_DataSizeConfig), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_TransmitCRC), (18 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_TransmitCRC), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_CalculateCRC), (44 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_CalculateCRC), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_GetCRC), (52 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_GetCRC), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_GetCRCPolynomial), (12 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_GetCRCPolynomial), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_BiDirectionalLineConfig), (48 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_BiDirectionalLineConfig), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_GetFlagStatus), (54 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_GetFlagStatus), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_ClearFlag), (22 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ClearFlag), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_GetITStatus), (126 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_GetITStatus), (8 bytes). + Removing stm32f10x_spi.o(.text.SPI_I2S_ClearITPendingBit), (44 bytes). + Removing stm32f10x_spi.o(.ARM.exidx.text.SPI_I2S_ClearITPendingBit), (8 bytes). + Removing stm32f10x_tim.o(.text), (0 bytes). + Removing stm32f10x_tim.o(.text.TIM_DeInit), (666 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_DeInit), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_TimeBaseInit), (322 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_TimeBaseInit), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC1Init), (354 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1Init), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC2Init), (320 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2Init), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC3Init), (318 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3Init), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC4Init), (238 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4Init), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ICInit), (242 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ICInit), (8 bytes). + Removing stm32f10x_tim.o(.text.TI1_Config), (260 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TI1_Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetIC1Prescaler), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC1Prescaler), (8 bytes). + Removing stm32f10x_tim.o(.text.TI2_Config), (286 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TI2_Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetIC2Prescaler), (36 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC2Prescaler), (8 bytes). + Removing stm32f10x_tim.o(.text.TI3_Config), (274 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TI3_Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetIC3Prescaler), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC3Prescaler), (8 bytes). + Removing stm32f10x_tim.o(.text.TI4_Config), (288 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TI4_Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetIC4Prescaler), (36 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetIC4Prescaler), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_PWMIConfig), (190 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_PWMIConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_BDTRConfig), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_BDTRConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_TimeBaseStructInit), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_TimeBaseStructInit), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OCStructInit), (42 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OCStructInit), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ICStructInit), (32 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ICStructInit), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_BDTRStructInit), (38 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_BDTRStructInit), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_Cmd), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_Cmd), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_CtrlPWMOutputs), (52 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_CtrlPWMOutputs), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ITConfig), (52 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ITConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GenerateEvent), (20 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GenerateEvent), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_DMAConfig), (32 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_DMAConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_DMACmd), (52 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_DMACmd), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_InternalClockConfig), (18 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_InternalClockConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ITRxExternalClockConfig), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ITRxExternalClockConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectInputTrigger), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectInputTrigger), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_TIxExternalClockConfig), (88 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_TIxExternalClockConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ETRClockMode1Config), (110 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ETRClockMode1Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ETRConfig), (78 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ETRConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ETRClockMode2Config), (50 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ETRClockMode2Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_PrescalerConfig), (32 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_PrescalerConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_CounterModeConfig), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_CounterModeConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_EncoderInterfaceConfig), (170 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_EncoderInterfaceConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ForcedOC1Config), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC1Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ForcedOC2Config), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC2Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ForcedOC3Config), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC3Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ForcedOC4Config), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ForcedOC4Config), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ARRPreloadConfig), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ARRPreloadConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectCOM), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectCOM), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectCCDMA), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectCCDMA), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_CCPreloadControl), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_CCPreloadControl), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC1PreloadConfig), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1PreloadConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC2PreloadConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2PreloadConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC3PreloadConfig), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3PreloadConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC4PreloadConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4PreloadConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC1FastConfig), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1FastConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC2FastConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2FastConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC3FastConfig), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3FastConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC4FastConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4FastConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ClearOC1Ref), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC1Ref), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ClearOC2Ref), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC2Ref), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ClearOC3Ref), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC3Ref), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ClearOC4Ref), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearOC4Ref), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC1PolarityConfig), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1PolarityConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC1NPolarityConfig), (60 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC1NPolarityConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC2PolarityConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2PolarityConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC2NPolarityConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC2NPolarityConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC3PolarityConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3PolarityConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC3NPolarityConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC3NPolarityConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_OC4PolarityConfig), (62 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_OC4PolarityConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_CCxCmd), (66 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_CCxCmd), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_CCxNCmd), (66 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_CCxNCmd), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectOCxM), (156 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectOCxM), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_UpdateDisableConfig), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_UpdateDisableConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_UpdateRequestConfig), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_UpdateRequestConfig), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectHallSensor), (44 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectHallSensor), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectOnePulseMode), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectOnePulseMode), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectOutputTrigger), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectOutputTrigger), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectSlaveMode), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectSlaveMode), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SelectMasterSlaveMode), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SelectMasterSlaveMode), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetCounter), (20 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCounter), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetAutoreload), (20 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetAutoreload), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetCompare1), (20 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare1), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetCompare2), (20 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare2), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetCompare3), (20 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare3), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetCompare4), (22 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetCompare4), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_SetClockDivision), (34 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_SetClockDivision), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetCapture1), (12 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture1), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetCapture2), (12 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture2), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetCapture3), (12 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture3), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetCapture4), (14 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCapture4), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetCounter), (12 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetCounter), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetPrescaler), (12 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetPrescaler), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetFlagStatus), (54 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetFlagStatus), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ClearFlag), (22 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearFlag), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_GetITStatus), (90 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_GetITStatus), (8 bytes). + Removing stm32f10x_tim.o(.text.TIM_ClearITPendingBit), (22 bytes). + Removing stm32f10x_tim.o(.ARM.exidx.text.TIM_ClearITPendingBit), (8 bytes). + Removing stm32f10x_usart.o(.text), (0 bytes). + Removing stm32f10x_usart.o(.text.USART_DeInit), (208 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_DeInit), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_Init), (348 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_Init), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_StructInit), (40 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_StructInit), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_ClockInit), (58 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_ClockInit), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_ClockStructInit), (26 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_ClockStructInit), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_Cmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_Cmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_ITConfig), (146 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_ITConfig), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_DMACmd), (52 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_DMACmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_SetAddress), (34 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_SetAddress), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_WakeUpConfig), (34 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_WakeUpConfig), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_ReceiverWakeUpCmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_ReceiverWakeUpCmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_LINBreakDetectLengthConfig), (34 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_LINBreakDetectLengthConfig), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_LINCmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_LINCmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_SendData), (24 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_SendData), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_ReceiveData), (16 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_ReceiveData), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_SendBreak), (18 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_SendBreak), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_SetGuardTime), (34 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_SetGuardTime), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_SetPrescaler), (34 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_SetPrescaler), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_SmartCardCmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_SmartCardCmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_SmartCardNACKCmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_SmartCardNACKCmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_HalfDuplexCmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_HalfDuplexCmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_OverSampling8Cmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_OverSampling8Cmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_OneBitMethodCmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_OneBitMethodCmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_IrDAConfig), (34 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_IrDAConfig), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_IrDACmd), (44 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_IrDACmd), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_GetFlagStatus), (68 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_GetFlagStatus), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_ClearFlag), (36 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_ClearFlag), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_GetITStatus), (176 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_GetITStatus), (8 bytes). + Removing stm32f10x_usart.o(.text.USART_ClearITPendingBit), (68 bytes). + Removing stm32f10x_usart.o(.ARM.exidx.text.USART_ClearITPendingBit), (8 bytes). + Removing gpio_stm32f10x.o(.text), (0 bytes). + Removing gpio_stm32f10x.o(.text.GPIO_PortClock), (528 bytes). + Removing gpio_stm32f10x.o(.ARM.exidx.text.GPIO_PortClock), (8 bytes). + Removing gpio_stm32f10x.o(.text.GPIO_GetPortClockState), (284 bytes). + Removing gpio_stm32f10x.o(.ARM.exidx.text.GPIO_GetPortClockState), (8 bytes). + Removing gpio_stm32f10x.o(.text.GPIO_PinConfigure), (222 bytes). + Removing gpio_stm32f10x.o(.ARM.exidx.text.GPIO_PinConfigure), (8 bytes). + Removing gpio_stm32f10x.o(.text.GPIO_AFConfigure), (228 bytes). + Removing gpio_stm32f10x.o(.ARM.exidx.text.GPIO_AFConfigure), (8 bytes). + Removing system_stm32f10x.o(.text), (0 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SystemInit), (8 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SetSysClock), (8 bytes). + Removing system_stm32f10x.o(.text.SystemCoreClockUpdate), (290 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate), (8 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SetSysClockTo72), (8 bytes). + Removing system_stm32f10x.o(.data.SystemCoreClock), (4 bytes). + Removing system_stm32f10x.o(.rodata.AHBPrescTable), (16 bytes). + +570 unused section(s) (total 23036 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch_hlt.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE + ../fplib/fpinit_empty.s 0x00000000 Number 0 fpinit_empty.o ABSOLUTE + GPIO_STM32F10x.c 0x00000000 Number 0 gpio_stm32f10x.o ABSOLUTE + RTE/Device/STM32F103C8/startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + iic.c 0x00000000 Number 0 iic.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + misc.c 0x00000000 Number 0 misc.o ABSOLUTE + stm32f10x_flash.c 0x00000000 Number 0 stm32f10x_flash.o ABSOLUTE + stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE + stm32f10x_i2c.c 0x00000000 Number 0 stm32f10x_i2c.o ABSOLUTE + stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE + stm32f10x_spi.c 0x00000000 Number 0 stm32f10x_spi.o ABSOLUTE + stm32f10x_tim.c 0x00000000 Number 0 stm32f10x_tim.o ABSOLUTE + stm32f10x_usart.c 0x00000000 Number 0 stm32f10x_usart.o ABSOLUTE + system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET) + !!!main 0x080000ec Section 8 __main.o(!!!main) + !!!scatter 0x080000f4 Section 92 __scatter.o(!!!scatter) + !!handler_null 0x08000150 Section 2 __scatter.o(!!handler_null) + !!handler_zi 0x08000154 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$libinit$$00000000 0x08000170 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000002 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + .ARM.Collect$$libinit$$00000004 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$00000006 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000006) + .ARM.Collect$$libinit$$0000000C 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$00000010 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000010) + .ARM.Collect$$libinit$$00000013 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$00000027 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000027) + .ARM.Collect$$libinit$$0000002E 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000034 0x08000172 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000034) + .ARM.Collect$$libinit$$00000035 0x08000172 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000035) + .ARM.Collect$$libshutdown$$00000000 0x08000174 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x08000176 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x08000176 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000007 0x08000176 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + .ARM.Collect$$libshutdown$$0000000A 0x08000176 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + .ARM.Collect$$libshutdown$$0000000C 0x08000176 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000F 0x08000176 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + .ARM.Collect$$libshutdown$$00000010 0x08000176 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + .ARM.Collect$$rtentry$$00000000 0x08000178 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x08000178 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x08000178 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x0800017e Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x0800017e Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x08000182 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x08000182 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x0800018a Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x0800018c Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x0800018c Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x08000190 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + .text 0x08000198 Section 64 startup_stm32f10x_md.o(.text) + .text 0x080001d8 Section 0 heapauxi.o(.text) + .text 0x080001de Section 74 sys_stackheap_outer.o(.text) + .text 0x08000228 Section 0 exit.o(.text) + .text 0x0800023c Section 8 libspace.o(.text) + .text 0x08000244 Section 0 sys_exit.o(.text) + .text 0x08000250 Section 2 use_no_semi.o(.text) + .text 0x08000252 Section 0 indicate_semi.o(.text) + [Anonymous Symbol] 0x08000254 Section 0 stm32f10x_gpio.o(.text.GPIO_Init) + [Anonymous Symbol] 0x080003dc Section 0 stm32f10x_gpio.o(.text.GPIO_ReadInputDataBit) + [Anonymous Symbol] 0x08000410 Section 0 stm32f10x_gpio.o(.text.GPIO_ResetBits) + [Anonymous Symbol] 0x08000424 Section 0 stm32f10x_gpio.o(.text.GPIO_SetBits) + [Anonymous Symbol] 0x08000438 Section 0 iic.o(.text.IIC_Delay) + [Anonymous Symbol] 0x0800043c Section 0 iic.o(.text.IIC_GPIO_Init) + [Anonymous Symbol] 0x08000484 Section 0 iic.o(.text.IIC_Send_Byte) + [Anonymous Symbol] 0x0800050c Section 0 iic.o(.text.IIC_Start) + [Anonymous Symbol] 0x08000550 Section 0 iic.o(.text.IIC_Stop) + [Anonymous Symbol] 0x08000588 Section 0 iic.o(.text.IIC_Wait_Ack) + [Anonymous Symbol] 0x08000610 Section 0 iic.o(.text.OLED_Fill) + [Anonymous Symbol] 0x08000680 Section 0 iic.o(.text.OLED_Init) + [Anonymous Symbol] 0x08000744 Section 0 iic.o(.text.OLED_Refresh) + [Anonymous Symbol] 0x080007c0 Section 0 iic.o(.text.OLED_ShowChar) + [Anonymous Symbol] 0x08000844 Section 0 iic.o(.text.OLED_WriteCommand) + [Anonymous Symbol] 0x08000878 Section 0 iic.o(.text.OLED_WriteData) + [Anonymous Symbol] 0x080008ac Section 0 stm32f10x_rcc.o(.text.RCC_APB2PeriphClockCmd) + SetSysClock 0x080008e5 Thumb Code 8 system_stm32f10x.o(.text.SetSysClock) + [Anonymous Symbol] 0x080008e4 Section 0 system_stm32f10x.o(.text.SetSysClock) + SetSysClockTo72 0x080008ed Thumb Code 290 system_stm32f10x.o(.text.SetSysClockTo72) + [Anonymous Symbol] 0x080008ec Section 0 system_stm32f10x.o(.text.SetSysClockTo72) + [Anonymous Symbol] 0x08000a10 Section 0 system_stm32f10x.o(.text.SystemInit) + [Anonymous Symbol] 0x08000a78 Section 0 iic.o(.text.delay_ms_simple) + [Anonymous Symbol] 0x08000a98 Section 0 iic.o(.text.delay_us_simple) + [Anonymous Symbol] 0x08000ac8 Section 0 iic.o(.text.lcd_show_all_ascii_lowercase) + [Anonymous Symbol] 0x08000b54 Section 0 main.o(.text.main) + [Anonymous Symbol] 0x08000b9c Section 0 iic.o(.text.test) + .bss 0x20000000 Section 96 libspace.o(.bss) + Heap_Mem 0x20000460 Data 512 startup_stm32f10x_md.o(HEAP) + HEAP 0x20000460 Section 512 startup_stm32f10x_md.o(HEAP) + Stack_Mem 0x20000660 Data 1024 startup_stm32f10x_md.o(STACK) + STACK 0x20000660 Section 1024 startup_stm32f10x_md.o(STACK) + __initial_sp 0x20000a60 Data 0 startup_stm32f10x_md.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __fp_init_empty 0x00000000 Number 0 fpinit_empty.o ABSOLUTE + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __arm_preinit_ - Undefined Weak Reference + __arm_relocate_pie_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __rt_locale - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_ctype - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_numeric - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _rand_init - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET) + __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET) + __main 0x080000ed Thumb Code 8 __main.o(!!!main) + __scatterload 0x080000f5 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x080000f5 Thumb Code 84 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x080000f5 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_loop 0x080000ff Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x08000151 Thumb Code 2 __scatter.o(!!handler_null) + __scatterload_zeroinit 0x08000155 Thumb Code 28 __scatter_zi.o(!!handler_zi) + __rt_lib_init 0x08000171 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_alloca_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + __rt_lib_init_argv_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + __rt_lib_init_atexit_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + __rt_lib_init_clock_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + __rt_lib_init_cpp_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000034) + __rt_lib_init_exceptions_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + __rt_lib_init_fp_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + __rt_lib_init_fp_trap_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + __rt_lib_init_getenv_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + __rt_lib_init_heap_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_init_lc_collate_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + __rt_lib_init_lc_ctype_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_monetary_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_lc_numeric_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_lc_time_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_preinit_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000006) + __rt_lib_init_rand_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000010) + __rt_lib_init_relocate_pie_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + __rt_lib_init_return 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000035) + __rt_lib_init_signal_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_stdio_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000027) + __rt_lib_init_user_alloc_1 0x08000173 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + __rt_lib_shutdown 0x08000175 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_cpp_1 0x08000177 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + __rt_lib_shutdown_fp_trap_1 0x08000177 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + __rt_lib_shutdown_heap_1 0x08000177 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_return 0x08000177 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + __rt_lib_shutdown_signal_1 0x08000177 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + __rt_lib_shutdown_stdio_1 0x08000177 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + __rt_lib_shutdown_user_alloc_1 0x08000177 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + __rt_entry 0x08000179 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x08000179 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x08000179 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x0800017f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x0800017f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x08000183 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x08000183 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x0800018b Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x0800018d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x0800018d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x08000191 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + Reset_Handler 0x08000199 Thumb Code 8 startup_stm32f10x_md.o(.text) + NMI_Handler 0x080001a1 Thumb Code 2 startup_stm32f10x_md.o(.text) + HardFault_Handler 0x080001a3 Thumb Code 2 startup_stm32f10x_md.o(.text) + MemManage_Handler 0x080001a5 Thumb Code 2 startup_stm32f10x_md.o(.text) + BusFault_Handler 0x080001a7 Thumb Code 2 startup_stm32f10x_md.o(.text) + UsageFault_Handler 0x080001a9 Thumb Code 2 startup_stm32f10x_md.o(.text) + SVC_Handler 0x080001ab Thumb Code 2 startup_stm32f10x_md.o(.text) + DebugMon_Handler 0x080001ad Thumb Code 2 startup_stm32f10x_md.o(.text) + PendSV_Handler 0x080001af Thumb Code 2 startup_stm32f10x_md.o(.text) + SysTick_Handler 0x080001b1 Thumb Code 2 startup_stm32f10x_md.o(.text) + ADC1_2_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_RX1_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_SCE_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel1_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel2_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel3_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel4_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel5_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel6_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel7_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI0_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI15_10_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI1_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI2_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI3_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI4_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI9_5_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + FLASH_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_ER_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_EV_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_ER_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_EV_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + PVD_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + RCC_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + RTCAlarm_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + RTC_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI1_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI2_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TAMPER_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_BRK_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_CC_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_TRG_COM_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_UP_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM2_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM3_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM4_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USART1_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USART2_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USART3_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USBWakeUp_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_LP_CAN1_RX0_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + WWDG_IRQHandler 0x080001b3 Thumb Code 0 startup_stm32f10x_md.o(.text) + __user_initial_stackheap 0x080001b5 Thumb Code 0 startup_stm32f10x_md.o(.text) + __use_two_region_memory 0x080001d9 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x080001db Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x080001dd Thumb Code 2 heapauxi.o(.text) + __user_setup_stackheap 0x080001df Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x08000229 Thumb Code 18 exit.o(.text) + __user_libspace 0x0800023d Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x0800023d Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x0800023d Thumb Code 0 libspace.o(.text) + _sys_exit 0x08000245 Thumb Code 8 sys_exit.o(.text) + __I$use$semihosting 0x08000251 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x08000251 Thumb Code 2 use_no_semi.o(.text) + __semihosting_library_function 0x08000253 Thumb Code 0 indicate_semi.o(.text) + GPIO_Init 0x08000255 Thumb Code 390 stm32f10x_gpio.o(.text.GPIO_Init) + GPIO_ReadInputDataBit 0x080003dd Thumb Code 52 stm32f10x_gpio.o(.text.GPIO_ReadInputDataBit) + GPIO_ResetBits 0x08000411 Thumb Code 20 stm32f10x_gpio.o(.text.GPIO_ResetBits) + GPIO_SetBits 0x08000425 Thumb Code 20 stm32f10x_gpio.o(.text.GPIO_SetBits) + IIC_Delay 0x08000439 Thumb Code 2 iic.o(.text.IIC_Delay) + IIC_GPIO_Init 0x0800043d Thumb Code 72 iic.o(.text.IIC_GPIO_Init) + IIC_Send_Byte 0x08000485 Thumb Code 134 iic.o(.text.IIC_Send_Byte) + IIC_Start 0x0800050d Thumb Code 68 iic.o(.text.IIC_Start) + IIC_Stop 0x08000551 Thumb Code 54 iic.o(.text.IIC_Stop) + IIC_Wait_Ack 0x08000589 Thumb Code 134 iic.o(.text.IIC_Wait_Ack) + OLED_Fill 0x08000611 Thumb Code 110 iic.o(.text.OLED_Fill) + OLED_Init 0x08000681 Thumb Code 196 iic.o(.text.OLED_Init) + OLED_Refresh 0x08000745 Thumb Code 124 iic.o(.text.OLED_Refresh) + OLED_ShowChar 0x080007c1 Thumb Code 132 iic.o(.text.OLED_ShowChar) + OLED_WriteCommand 0x08000845 Thumb Code 52 iic.o(.text.OLED_WriteCommand) + OLED_WriteData 0x08000879 Thumb Code 52 iic.o(.text.OLED_WriteData) + RCC_APB2PeriphClockCmd 0x080008ad Thumb Code 56 stm32f10x_rcc.o(.text.RCC_APB2PeriphClockCmd) + SystemInit 0x08000a11 Thumb Code 102 system_stm32f10x.o(.text.SystemInit) + delay_ms_simple 0x08000a79 Thumb Code 32 iic.o(.text.delay_ms_simple) + delay_us_simple 0x08000a99 Thumb Code 46 iic.o(.text.delay_us_simple) + lcd_show_all_ascii_lowercase 0x08000ac9 Thumb Code 140 iic.o(.text.lcd_show_all_ascii_lowercase) + main 0x08000b55 Thumb Code 72 main.o(.text.main) + test 0x08000b9d Thumb Code 22 iic.o(.text.test) + Font6x8 0x08000bb2 Data 570 iic.o(.rodata.Font6x8) + Region$$Table$$Base 0x08000dec Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08000dfc Number 0 anon$$obj.o(Region$$Table) + __libspace_start 0x20000000 Data 96 libspace.o(.bss) + OLED_GRAM 0x20000060 Data 1024 iic.o(.bss.OLED_GRAM) + __temporary_stack_top$libspace 0x20000060 Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x080000ed + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00000dfc, Max: 0x00010000, ABSOLUTE) + + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000dfc, Max: 0x00010000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x000000ec Data RO 654 RESET startup_stm32f10x_md.o + 0x080000ec 0x080000ec 0x00000008 Code RO 682 * !!!main c_w.l(__main.o) + 0x080000f4 0x080000f4 0x0000005c Code RO 847 !!!scatter c_w.l(__scatter.o) + 0x08000150 0x08000150 0x00000002 Code RO 848 !!handler_null c_w.l(__scatter.o) + 0x08000152 0x08000152 0x00000002 PAD + 0x08000154 0x08000154 0x0000001c Code RO 851 !!handler_zi c_w.l(__scatter_zi.o) + 0x08000170 0x08000170 0x00000002 Code RO 709 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x08000172 0x08000172 0x00000000 Code RO 716 .ARM.Collect$$libinit$$00000002 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 718 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 720 .ARM.Collect$$libinit$$00000006 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 723 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 725 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 727 .ARM.Collect$$libinit$$00000010 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 730 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 732 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 734 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 736 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 738 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 740 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 742 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 744 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 746 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 748 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 750 .ARM.Collect$$libinit$$00000027 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 754 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 756 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 758 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000000 Code RO 760 .ARM.Collect$$libinit$$00000034 c_w.l(libinit2.o) + 0x08000172 0x08000172 0x00000002 Code RO 761 .ARM.Collect$$libinit$$00000035 c_w.l(libinit2.o) + 0x08000174 0x08000174 0x00000002 Code RO 783 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x08000176 0x08000176 0x00000000 Code RO 798 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x08000176 0x08000176 0x00000000 Code RO 800 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x08000176 0x08000176 0x00000000 Code RO 803 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o) + 0x08000176 0x08000176 0x00000000 Code RO 806 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o) + 0x08000176 0x08000176 0x00000000 Code RO 808 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x08000176 0x08000176 0x00000000 Code RO 811 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) + 0x08000176 0x08000176 0x00000002 Code RO 812 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o) + 0x08000178 0x08000178 0x00000000 Code RO 684 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x08000178 0x08000178 0x00000000 Code RO 686 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x08000178 0x08000178 0x00000006 Code RO 698 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x0800017e 0x0800017e 0x00000000 Code RO 688 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x0800017e 0x0800017e 0x00000004 Code RO 689 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x08000182 0x08000182 0x00000000 Code RO 691 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x08000182 0x08000182 0x00000008 Code RO 692 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x0800018a 0x0800018a 0x00000002 Code RO 713 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x0800018c 0x0800018c 0x00000000 Code RO 763 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x0800018c 0x0800018c 0x00000004 Code RO 764 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x08000190 0x08000190 0x00000006 Code RO 765 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x08000196 0x08000196 0x00000002 PAD + 0x08000198 0x08000198 0x00000040 Code RO 655 .text startup_stm32f10x_md.o + 0x080001d8 0x080001d8 0x00000006 Code RO 680 .text c_w.l(heapauxi.o) + 0x080001de 0x080001de 0x0000004a Code RO 700 .text c_w.l(sys_stackheap_outer.o) + 0x08000228 0x08000228 0x00000012 Code RO 702 .text c_w.l(exit.o) + 0x0800023a 0x0800023a 0x00000002 PAD + 0x0800023c 0x0800023c 0x00000008 Code RO 710 .text c_w.l(libspace.o) + 0x08000244 0x08000244 0x0000000c Code RO 773 .text c_w.l(sys_exit.o) + 0x08000250 0x08000250 0x00000002 Code RO 788 .text c_w.l(use_no_semi.o) + 0x08000252 0x08000252 0x00000000 Code RO 790 .text c_w.l(indicate_semi.o) + 0x08000252 0x08000252 0x00000002 PAD + 0x08000254 0x08000254 0x00000186 Code RO 146 .text.GPIO_Init stm32f10x_gpio.o + 0x080003da 0x080003da 0x00000002 PAD + 0x080003dc 0x080003dc 0x00000034 Code RO 150 .text.GPIO_ReadInputDataBit stm32f10x_gpio.o + 0x08000410 0x08000410 0x00000014 Code RO 160 .text.GPIO_ResetBits stm32f10x_gpio.o + 0x08000424 0x08000424 0x00000014 Code RO 158 .text.GPIO_SetBits stm32f10x_gpio.o + 0x08000438 0x08000438 0x00000002 Code RO 19 .text.IIC_Delay iic.o + 0x0800043a 0x0800043a 0x00000002 PAD + 0x0800043c 0x0800043c 0x00000048 Code RO 17 .text.IIC_GPIO_Init iic.o + 0x08000484 0x08000484 0x00000086 Code RO 25 .text.IIC_Send_Byte iic.o + 0x0800050a 0x0800050a 0x00000002 PAD + 0x0800050c 0x0800050c 0x00000044 Code RO 21 .text.IIC_Start iic.o + 0x08000550 0x08000550 0x00000036 Code RO 23 .text.IIC_Stop iic.o + 0x08000586 0x08000586 0x00000002 PAD + 0x08000588 0x08000588 0x00000086 Code RO 29 .text.IIC_Wait_Ack iic.o + 0x0800060e 0x0800060e 0x00000002 PAD + 0x08000610 0x08000610 0x0000006e Code RO 39 .text.OLED_Fill iic.o + 0x0800067e 0x0800067e 0x00000002 PAD + 0x08000680 0x08000680 0x000000c4 Code RO 41 .text.OLED_Init iic.o + 0x08000744 0x08000744 0x0000007c Code RO 45 .text.OLED_Refresh iic.o + 0x080007c0 0x080007c0 0x00000084 Code RO 47 .text.OLED_ShowChar iic.o + 0x08000844 0x08000844 0x00000034 Code RO 35 .text.OLED_WriteCommand iic.o + 0x08000878 0x08000878 0x00000034 Code RO 37 .text.OLED_WriteData iic.o + 0x080008ac 0x080008ac 0x00000038 Code RO 302 .text.RCC_APB2PeriphClockCmd stm32f10x_rcc.o + 0x080008e4 0x080008e4 0x00000008 Code RO 664 .text.SetSysClock system_stm32f10x.o + 0x080008ec 0x080008ec 0x00000122 Code RO 668 .text.SetSysClockTo72 system_stm32f10x.o + 0x08000a0e 0x08000a0e 0x00000002 PAD + 0x08000a10 0x08000a10 0x00000066 Code RO 662 .text.SystemInit system_stm32f10x.o + 0x08000a76 0x08000a76 0x00000002 PAD + 0x08000a78 0x08000a78 0x00000020 Code RO 15 .text.delay_ms_simple iic.o + 0x08000a98 0x08000a98 0x0000002e Code RO 13 .text.delay_us_simple iic.o + 0x08000ac6 0x08000ac6 0x00000002 PAD + 0x08000ac8 0x08000ac8 0x0000008c Code RO 49 .text.lcd_show_all_ascii_lowercase iic.o + 0x08000b54 0x08000b54 0x00000048 Code RO 2 .text.main main.o + 0x08000b9c 0x08000b9c 0x00000016 Code RO 51 .text.test iic.o + 0x08000bb2 0x08000bb2 0x0000023a Data RO 53 .rodata.Font6x8 iic.o + 0x08000dec 0x08000dec 0x00000010 Data RO 846 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08000dfc, Size: 0x00000a60, Max: 0x00005000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 - 0x00000060 Zero RW 711 .bss c_w.l(libspace.o) + 0x20000060 - 0x00000400 Zero RW 54 .bss.OLED_GRAM iic.o + 0x20000460 - 0x00000200 Zero RW 653 HEAP startup_stm32f10x_md.o + 0x20000660 - 0x00000400 Zero RW 652 STACK startup_stm32f10x_md.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 1370 0 570 0 1024 5129 iic.o + 72 0 0 0 0 1547 main.o + 64 26 236 0 1536 836 startup_stm32f10x_md.o + 482 0 0 0 0 5730 stm32f10x_gpio.o + 56 0 0 0 0 7058 stm32f10x_rcc.o + 400 0 0 0 0 2988 system_stm32f10x.o + + ---------------------------------------------------------------------- + 2462 26 822 0 2560 23288 Object Totals + 0 0 16 0 0 0 (incl. Generated) + 18 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 8 0 0 0 0 68 __main.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 94 8 0 0 0 0 __scatter.o + 28 0 0 0 0 0 __scatter_zi.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 2 0 0 0 0 0 libinit.o + 2 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + + ---------------------------------------------------------------------- + 296 16 0 0 96 584 Library Totals + 8 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 288 16 0 0 96 584 c_w.l + + ---------------------------------------------------------------------- + 296 16 0 0 96 584 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 2758 42 822 0 2656 23684 Grand Totals + 2758 42 822 0 2656 23684 ELF Image Totals + 2758 42 822 0 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 3580 ( 3.50kB) + Total RW Size (RW Data + ZI Data) 2656 ( 2.59kB) + Total ROM Size (Code + RO Data + RW Data) 3580 ( 3.50kB) + +============================================================================== + diff --git a/Objects/ExtDll.iex b/Objects/ExtDll.iex new file mode 100644 index 0000000..6c0896e --- /dev/null +++ b/Objects/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/Objects/example.axf b/Objects/example.axf new file mode 100644 index 0000000000000000000000000000000000000000..7fba79ad69920ff31fef5d0c7a81dac7d6f15830 GIT binary patch literal 39300 zcmd^o3w#vSz5kh=ncdB9lHHI10Z|u7HCos_Km;q0&5JxqOafXLnu|h`ZZ;Uw?-p*JXzBU_E7cw8{g)Ez8anZFd z=G!eX=U#m8!S@UJei7d<;j7!y?_U9JzeYcR`-Av?^?%WqjoQZ8X!%&)eYd^LG9Rk^ zYUPnC=@)Et$=IQnJk-j zQT$}h6YjOq6{kOP`eWWlypOTblChlX@#DwG+33-?*=W<4{P6hk*T&^H zwj!g3t$6q7#6P7*tySyn^%Pf*i#e%`*DB0MWx3WazR?x*H(1R^=Z!s3t+L+g)@t9V zgI!sjf6({H`0?M3KlZY(tZ9_l@pa(q#MiyAdf&^3GmPKaqYml%>gWpZBTDswf3R)7 z>c?L8mW?03{|V%?hUeBN)#m%Y^7y+)&tNv5|D6XNBleq^PaRQ4|#C8@yVddyBvi}e}nsO$+xr2 z25q*}w%b{zj3~QoyLXnK{R@)W#%v?D-5yA=5w=^}wX;GRQNd?#Nv}$*@@#q!AGN2Ohk-OjZBw~>PZIbiEc^ge|_BfqM35Mkprfrt#xy-tKTjFT1eiEe}97BQ2N3L+ffz{ zlm*!lHXVh9ygcmeVDaIH*r?-83?d_JRDRRzW25X%w(I&amCLGZYoVLV!oq0Qo20Mu zG^ybG1!IuUyU6E`uW%oaQ(>`^Px`|eR_=T zVx!+1D??pjqfd=p0p1g1<31Va(XqWi-x#|O*GIcaJ^~F2KgJtu1EOVu{>ONjvc`D z$}t&rpeI@8Mo&5lOEez{e?^dX%FlYr*JuxNkn-);!aO1CEqiS(d+Igxs;@lhg`d1- zYuIStn9*nd#XacY{&cXXxd%mQ!JZdo;G=T9v{2Pb%ULL)2F!nv%D}hydbCbTrOZo8 zW@@32%YphznN;@1L&b;Rpx6VbJ#z8kHAsUGX_Am8NqXg}9N6~FtlZf~DUx{_WOf8; zh_0YI&+F0gPrf_k8$Uk%-SOkMzsnGsg3xE)rBsa{&qVk-dYI>$ct>V6sPEEe1Fz*v-+9d@IeWYn&b7`Ljg%2k(8788 zXq4Xe*p7oVrr1UT$dS-0JGQNuq(EVyFxJD4G4u$cKZW*gs&z}gNxl2Q*Y8@J|AYjL zn0Fm^u);r}pH69RlUbpRzDh#Pw7sbJWm4e|t|%_QtrJU*=rv?P+>rJpQvc-ss3L^8)#f zZS#34SLoy^jZU7MremiAjUQh=zVZ#{1wVxknnu}L=UTm=5uOa3Cf!ts(rh|*X%v0R z*y~!oPH}s{r51!M#s(E*Erq0FHuA>Nzwr_leK+&%AIoO@$1+)H_Vr_Kudt9&xDfSR z*Y{|(J{z?>6E(?=8rS~rW6*OJlQt;4Zo7HtvO)zdD1=tyMyt_deGb-0_A$idg;pkb z64E1$e4mdb+a9?JHBBAyqOM4@$B*Chu0$iq1@cY%$Glz{X`6!9n#)Ap!MHo3V0`TS zrx;6?VK!((yMOoSHq6r+-yT2Sk5+Ia`u!ihLsYa;{t436fj^eF6@RSY?5$@{VRLhx zo$J`5+EsI!8B=AFnKdVXYhcbSNII7}^OzG?OzxYDL3YxIv9)Uv_IaI(jV-&NwrUw; zPuLD-juCgc4k#o)e?4oU2SbKlRlM!7#7vm)-Gc9+S;>DV{FkP z*kP;b>dd2f^XNmd=Q){8x*)^ON^3U-ma#24IXPR{R<64&5D3g+TXC7iDFL=MBO^m% z%L28vm$I!$;8s}J3TwWyz;X!`GQG77AGXz&Y1_)SDo*cK$OmAVbnOUVF#D4T&p4}^ zRU?)XbYffae6$=&%h~C^GT-S4FGjc{&zaZ39L}iI!I0gm3Pwr6(-Lg@5N`mHD>lid zux<2VOjeOQUt3$-5ZhW)S-F@kuB@!|(Y0nPTMT+Wb8g9yY%H^-r3LA6D#{RJm6w-M z`YV^hytl9tCIaN)%}PGFo4E|xSeZ^i$BxRa{_C_bDNYSeIz?q zm9xFmPsz@aR!xWCLMCU|<}ROcp8I2NTRt*7jn(GL*#zN+0&thP-3Y3ZRGW+W*=(@S z1$LZ)01Evae#;<1w|f~FE(L;aHw?gS?n2OKVP2Q%;c{6?>tJT*O1hjUizkDW7Q==Y z993AzF>s(W#m{o2DfY5_k;F4+ET6$xu8F9g2~wUPnN7-pL~>IXGMi9TDecp&GVmU> zWamemr#PW4dF^nJpUE7MZ#n-2E+mg}2MR|ix}#L#D7$c!Bk2HS)0uMb$#$U0BW{uX z9BY2bCsS0DPjam?R5##Gv*)Io%)`4vYMPZys?)VnMt<{?W$C6;CTCA@rm^@m4Q^PxBCE;m)798-=p znJGzUahVA&}DXx@5la{#D2Xy6xrhS5%Y4nF9RV8`t6m2>q>2x^QrI(63 zNkvh7zy>ag!s0$&A5EUnJer&I7WZhXHgagLjhf0dH}3#Y|EvZ@UClR@oYq0iFv)7f znaRj`A)I0^lUZgJ%EGB;(?mKg)d)^cR?4)EU<&m)Nyoz7lQ#lW`H2?cOwwQ>Bh?~Y z$;f$&aEoHdH01$4r6gx1^U0m8ch)HCRA()6K+}qGeB@B9zoX-$Oxm11C5vV%lEdbZ zor+U++MN!J>KRU#)9uJ~W}~`LXNnIEOPHsy4{L+Q)n?ehRQ^NT*a_WZ=s4PN_u@-= zQJ6yc$fQNn50f^lj*a^S!@T6QIVbqU$$gSu=e_-i5u5!O-!?aM*5F>A?Yu#{+E$+J z6Fw#$eH45tZ-jSY3DJ)`WSOo%1e#CKgg%6I-ua5fHh5HiWNR^ao+vGqD5ix*J%i1m z_uyf=;2b!C-Zt>QW8@(%Fw1?28>2c{o~GZ2wqbD2PnVm zjPkILX*jok2kOSO6fda*63dee{wYlPm3TApP5RCde;b})ui|>XWSU5x+A-xpPv`S^ z64m^eq>&t&ze$d0??mdhBSGFize86 zzqA;y&*rjRY>8tZ+P;+r5%#ap(xoq5S?F?^i0{V~DL&*Yqn|`N%>Fd$y$JbT7%QE) zlO4i$X=A63@3!E3E%-hQzTbksY{C01_yG$(Xu%I@nA$4k(~Ews3wNy_O7>}gL|ITi zbh^x;F{VDOtRw4RFDw{y=mL1?#=d$noRQK=s;OYJ+*-8U`5jxGlG@ibLl^hzgafK9> z7mcd)p%F&^V5yq1bMdw96-z&IIlv?MN@dFZxH%Nt_Yi`#RCpo zOoU|$^T;|_t|%U-4$2g#CsPLjCDSui2jz;_bD9n+lswNzbWo|}d**Ev^81)jJLu96BpLpr!xn&-J(2Ro%= z&vqSLBQ5mo)WN5v#h&YRaIJK{=Q9AGp?I#7$~@S*7g@Mos_~%l3UGte;Q1oJ9um7z zYW85ao_(3Xh_u%8b%3uCxJgQQo&=yGQa&T?^n4$Ir-*a2bY0Fbbj~eUp=1scQmKCM zx{}FM@*EH2R6#PV7{V%3$@^T!7;b0sZ=w6&Feoioevg~OmiZ@8vR=i-hp&8>oLwMa zFMEz_X^?M}ndhH67?Dx6AjYfKO|sKNO@xEb$awD5#cr0p9=Fc9Mb7hN>)=*7-!okY zx5=|Sr|95z*~g~nos87(2i^9oT)lUZ+LsXFZi%`hMtz9XUPY7=X{zm}%=HvpAW^0P zoe>jMHl`q(ruRWo`zMHeL?(UmqV0K^azgqeDTv((5M?$OS4C=Rt17AtZ|Lm^7qzxE zE-0-oDPB;qxG0_o#S(+jU_8;kptP%`cqrK4>5sFDNPjdk5FSXJ=L^L8eFS^^!ZBZ0 zB<8E?Ul;D|40rk#`AZl0+9Hv@^L%(}3&s0=pEw65N*5Ftx3h}#)~t$$WAQcJLz^P; zHIo4K2I(+FG*nh;Szc5mB zZ0=_`^>>`=_&M}mrC^!!kGMIM%;!PLdKniy0j36kx4?{2&7}c=#xM?O0Kjs(05kyD zbwC4vM+YLUuvF)|eoSzIQ~+UNV><#;`|V`IuM!zCd45e&ewE4>Hk`jFSgcaSfXW{T zmgrFa8^Kbp%Xq?RGB341OePyC;f~`Z(I{!=m>aR!nk1eNu0XR(sr{Fv5F!P63Q2^d z^C^`ElfNU0O(fy`C`oMMHUO0+DTow`7%rO-!z-jel8Rx(5W_s4hBruJfsIV!ahHNx zriICKIAl{H%L`3vcc_r6vr*P~LWP-Ah#KT(R*{*Y*-S{7F({l(3Y)mXTAmfN!es^p zdTf!}&m)DKQwlem6>c>s&@+wHUPlU#l7iezF+9rC3~1xde$951iw zH*k}HnNytLCZTht2`U9CDDtqF=i%FAy-%uvy`-K|vJD zIi&CmDTso5#vmb@cMVCrl#+PKAR%mYkc3So8>=Z>Hr@g8bq@YuDYbu!BtD_?&QG{v zD^V_0i&1{0$E)_GddFqsUDIaHHP*6Sq;x-zh%4MLBFY+uhp$BsfN?2nH^N_{ut$V% zgbsxdfPM;MlXGmDjkr55!i5G_W#RNZWq$qvKq_ygh~;BdOoWS-{GaLJ5@-JJ^>Ars z{@?ZR0*nIWc7@TTOOZYao0;rxTxVxtfja{>@hL_Hww;fFB<0xT6-1SraFv*{1UILo za;9yGyqc(TH?B5$Bd$1YBUsh)PCzE#hN~j)!?jR8glmob16=du-{R_(|AOl*`7K=Y zb;b3v3%j=P4z3cjKZvm7Fg0n4~DqjJp9SQb|?vGxq6X zc4ZdJB<-xP;i9nY8^Cco>_l>`z~u>GNwQ&&8U6&8+MfbNS?{&oG)v8-&^}`E{-0Jf zrS_i^e~(9B#+2G$Ai}<+!ah;}%6F6czDLmkpt|Sv6MBGB2;|*lM43B`$a$?1DK`>2 zpy{#Ol1NMmX7MDwOex5a_;5-B84|_Hrs_+mQu`Q5rF@B= zi>KLclJ*ds$%V!ENlUI$dp0(2lwvMLF>xEk+=h@^$fahJ)N*r7%gr$@H^&s15EE_h zDyz*gtrjum>dUxNdjm;@Dc2%DVRI~DuFrDyHD0Ox=yjK0ppf5W9uaN#r zq%Z%G6kd|1CbLBA)l&NtBvD|4MBY0jQDCDq0OoRq0vjnHhD@HqGdLH}=|sn(@%O!g^U=VC^B8SeD?0mb(P0RHUeR^^AV*CN+~ zqpZax$gg&$t^}}u9G6ESD=l;E#|>M7-=>?x_AG8gVA?KI<+TiF7D=3|I{9@Q%OG6| z!=URwA8SH)G0YoV(R*BaM4T=QIU zT)nOxxXyCjf@?mrk3;@J1f?>^y|_6Pdk!-BG*Om24iUwcc`7JbXW=pmEWd>#KJu%w z=a&GV22sXnLH1fQp1B^zVqdLH7Dx&s0eJTzSk+Wmk|HpRDH8kYX2A!9+|4|aAK8+2#2TW+nQ4QN+LXs zC_Nj<oy`q9gOirHCA4Mr9Hk~ei!57b{q<4g*p*tN1@-zgMY24ED+!85t z;R~{tTY6Emq;HT)?U#_HF_MOmeV8o0MToCyvoZvv_KhTyCD9a-E#j1|M42wlsKg@r zLQdI9l-bfudaxiPvn6h2hQ2i_wSSf*=5q<2#QBiWRTlGZPc_NZfy_*totF#d{00xz>5ZomqqO-%zA|jcW?rtrjS^B=O)P9uW z*(*Uco5ypvWJg;B%;fPTp?g0WzK6#%?RjjkB!pq*Akn`dQN5Y=7tk97o$;LA$LXM) zs_!OC?FuP8DA`M(5k^?)JWWw9KD_`zidtF2PM?qP#b7Hz+v#-(hbfGH*nSsGEhe31 z_D2zHqhOQcGTcufpISh*P$GFr1W4@k2^L5ue0NTi)`MRrE2k0SP z3w3}V(zRFz=pkL_>i|8ZE1(1Pkgh5nP!Gw+uuR=4SWy5|ajZsUS?Chh63T1`La`vM zD)t_LuOMja%*N>Hxdg#4fsN7A6G!+aurYdiMi9P(!c=NBdTt?|Wp)}pKTE+TwweY= zRtX{eAn~8sS#$$HDKN>rl+4nvWMjd(h%Y!7@df9iKr~tzN`#6UA|0W=A}nGTHHSLZ z$BXL2y?y!$_|Qhxl|+2wCu?pLSTr+QY2dL~Em z9hV=10``26f)Ww&-!}Wz)9mstdAm9nstch4qkE9TVxDNp?tT`JlUn9!cSSzpkklMx z@FS3S+wWH8EA8^+=k{UF`~{d(=BR6ySrx8m zQ1)cQBAmV@6;bU)jBJ6~$v6@3$SFo?0Qvhw97w)N{(Ir2KF#K=nZo1 zAd3dJpiVt^j~c*gxct4#_n?6tviT9BmL-47=C{|$-?_XFO;LUvx^lf;eiEhtp8|CE zAbsw-R2%29Kj5NHY#4DDsTob`6vXH7+l!Eq9}IR;Pj$#e?G@J0%rlAp9YKFQMMpG) zyjOTi(B#Jl>(C*|-*cfwlEFHhS1nQtUymUS{0Z-7 zht-_Ds>|+2Z#5mhhSe-|er}jV^DeSv>OZ04clDw#-II>}rf%_G&0^LL-UFi>MJhb@ z9^Sd8u{(m%z>id(!0uNS@@01_rLc=6zn8@yLS?3FSUsIQTxY3TzyIL&-u&PyH>)Q~ zHEMr)|2_&8hwE+>!aNL6XW7x!+q>08r923~?XZ-`vyea2wGso#_H^a(&Iwa+!jgE* zE~#@|$BR`Ljk9&~H#a$b>KPbUQR0pwyZrDbKf#}Kn6A~m00Tv+B6E@WG$s9au)Roe zmZ(A9mJGcEb}_UI(raIbfs-nNHZv$W!Q{X}lY;_EqP?hC4`6f`L+pJRFyF@%;bZm& zbqQ=>G(Ur83CR2}U;wj(Z@>T*;8HY{k3j-+oI;u?6se0!)P*`hergCU)J{WnNh%Gu z!UQHXqcEY(Xh@H&VW6IcAho=VJ*p4waUOzYh^9_Gtqw|JI)OHyPQ$OxhQNGiEcdJD z*Quv}Kn=foIwdS!95Yg>ngap9NYygG>Z?mv!uR7@#^JgebvO?m%z-dJ^PlfyxO@3Ml51Qq9$NFC%P=0R)rHAZKgZ*61K4xzeOk@A>2b6yX^6yb) zUjq9*y3FkuCeC)PR}0fu_~-a2vO|@IEnV1KVt7%rp3v%%Jf7&H{(cy>k-Go46TJJs z8ql4#`@i2Usb{(RFtar@)OQ^;ox1Y`)2aW7N1qQh$FV%i{X1uVre`F2kV?*vx}&`j zOn>kg^)Jl0@YH3o*dd<1aGVX6F`;?|+fWYICH6h?$kr}Zwac%uu3=OGnpEtOuNAc8 zM%q<^_O_9Bg`iy_8Fb&?!tGsUq#YNuYc*O%3E~(94ISNQBzj;#)%)uf@oaFLbVzjX z$+Yglz9JXcE<}PAS1`h%>S=)1V;&PnS8EZ# zm`%}xSP_5n0*_`Y)4~co$`D8q$0wG~h;zkS8T;enfB%Or9+w5V^}L)^lD2_9C!9%Gr2Kq#?>tB=Xgh z%oh~`q_liV`t&kcJ+8t0QFb-JY8TJ>>2Mf%fQl?NmmqQ4ZIpLG-0iwkbvC2KP@?cr zo&4hEyc@h*o2UOyJSE%*=rYdJlW`t|k*S!F%z_2k?-oz9N|ODA9!HZQjzc1jA82uW zUBvO@6UOoD6UIS1jPjqr&T(ChtYU@2IPa!Z(3Yb7IwZWBM7C9e_X5{o2JLVihJ{>= zaw_h;RTNRHAOxSogAJ)h$F=T)me+L^k2$^F1CYpcJ*v7EqOQUy3YwN*kjyElWm<}J zc#u;w5Tr(e=4l9;3y(+r6V33HtF>o^>31SP?P-|by=c+dFqB61C8!qRX<@Dyz_o{z zWRcy=r|Ng|M)MKAAY->Lw9Ef-*&#Gt`2nSiFR7qjVM2EqHD~!Djh2l`cM0Nji#Zl$ z*opjT6SYiC_q@-l@-TW<)%Ptt+0@ZvjTaRZYcxnMI5{QiOc8 zJXC&K!BZrJ8+a!(uS?A%0eG-mr6|4y*KP;m1?Cmgd24CC$TRk+dd32@#X5CvojQ{q zDltzK9g|$A7Vc5cg~c|oJL=R6>eL$4YLI#R(I(qTN4*Yv^HKFbYJ7U=#h$9d&OgBn zz^bz_R3~hLsQ*r^6_5$S_KvdD!(bQkH_ezbeIez@MC1r^#z zln?6y6WFw^C_fE$Hacn=h|x=9AkIR|sFNSwvKk z5n(E!o+@J&t70@jFCb@WeKV~(^Dg8F%x1x?>YSry_ZX~aqX}d<2kX_WJJAsE@HFF) zd%Pbn?8Qd<6ow5UClkUP~(>QIdfJhW3OkMY>y zNavjTJL?E<-oBS@E+D~kexZ` z_kBPaemfF4m6i|SSa`G!1E)Y4$nm_7LT3*WfE5dQ138#KVqq5`ReNb0RQ@4PNq0|A z_l};P;hr6IBV_pNF=v$f;a#X@xSmB9ig;0Wb*i6Auo$oq(bMFs0EF%8%wMagBDGy0 z7f&FgG7YEFLz}2F4WCo6us|aa&Auqd-G&@b>%m}zr)r+#Gr*b!H17~C%wtAJSzkC$ z%X*1=wv2~-J?j~UtkYJjd<&wYJdg#<*N}%Zy3qL-V`j&VO@Vbv22GagFpulT8djZp z_G|P=pUdN)c1X>yQ%|KhiqzTj^r%Wwd7`~m{8EKl9W9n%oPwF`2Hdc30X@I`+-5%0 zybl{0G|JLO2dR$k-H6wbtq~{_5=1hh3Yh_NkO}lg(@TI*s+Jd6iL>~%g zgD%kjzALRDQJ((YDW^x&BY5V}jxs5SF!g5i zB^~N;r~*<;r-Nm>+=uvuS4UrHpj-UL3qSF~Z@kj)AFfHWV{Kmcd9PoC;TKZa?xqd& zioQt4dNw!^@9iE4clxj)&IWN=P#R3IKuvjbEFAA>3$4R1$dWQ0J)syES`3+BFwoKx z_;|3j_Ts8w+sB)$fo5Zv5MwZwUw-v$gA6$pj6uesaBGtdrdQ4h+9#OOATEr>C)I( z9e_!?1PIqw2Aiw-ty0_q;s!ZRt!;%QWuRqsRb?@v4ZysP7qHegm|4yD+sKs+cFI<|pl2DjBto$}q1j6hzThLJTHQw?BMu~;Og z6+X$Y2q&uhLfsn05F}=x^OC`MqNcUBBGlKrE*47kMg~@g`Ub*=UT!09Knr+yV<(lL{fBO#XLMy`?DKTMIJvh)o)hg5{Fd0StG1LyA z#=$O4@}#&4ox80}Cs;w;n%ei!9!5E13ggw-IG`(SvWV-u@^ssZu} zYQd!jEUKV^ApDFGHm;9j6T4`*CEmf4m8@n0C99VXwTi+aiu}X;e*Ax^59dombWF&& zfc9P!lw_yJCmWU?cSUn;Q?NA}4tEAiiW_S#Wd=g21)q}=XpD4*gMr$WLY$-8m8i%~ zfwtO}D~#0UN)uXTKuv>*V3Uze1U&HYB#0QQ%>sdH;-h^9#k`0@Vs6xsnm|~_jvCBU zFnhqaytM@vd>bn2TSP2+RZ9BEGBD8mjizQ*t1$>Q1~AR2x~Q!d;Sad240ra1YH6y~73wf@hlDM1PAhj)(zXcj+RTHZUh5^mW20)tdAxp^ zSY%KqU}T6PSN$Zdg`>R#4Bu!Z&giT4!Jyzp66*~eHoS)6ohoU7cgn08^I4+MtWtOZ z1g*o=y`sSr_UK%WyN=A1(1l0K=~WZFbyB)BtjVttE7kA6uc?j_$v|P?BotTq;@`@KpD{`lrrtUuYBK*Wh4081LmTA`!ShiEC>y z7o`rJcN~N&xgLcuGr(h&2t}eIfayxGd=n-RM5fLpg=o?n4B&B=So(b>1$cq+9sy6} z{dn(*fkM5LfYrTtcH*KuEj&~i3vF!f9SUoVmT(t_>mDK1+7sDWK@Y=y9i2h=X=5MAeUXjfSVt%xW{GedkA`v9%lfr`E7c1O#zeyoqLVp!9RZ#XLySrjlSr26 z?GHx=6RZRMSv1s*t|8Kg->_|>dnCp>dgzNhbl}Efk&P#%8Da@=jkZAd{@Y=)%Kcv% z^OG4m*)5A)%L|z1Rl#0bFwi^YlUIxMH7xy(Rb2XLYg-ckFI9gvVEp2TUaDr|HybeV zA2(q7dE{>lnD}K_XT%L3VV_>Qreoqa7%=J6OW1Tir7yMiCef-heSG|iV@Uk<2m)Z$ z_|@ZW&xWm|*;7WrxmCi{AMQ+yX$`1EQXs!wE}_(K-{jliJs@=nL6H>nx@gk&#Wdi0kV694x?-?x^>Z=2xXKZ1`R1t;xU!XhX+K2aN7F=S%6&6hOSMP5rJyyQ8 zeohvjwfO z$%ti~9X8@KEx6u-BNj~WZ6bX=KVJvdKjfdu(mNU7>Q5{F;Yp5fvh+;Gf6kJge*hoD z_^<{}q54T@wP}8#`zwq0Ou}R2uQPz#z^C`Nko*Dz-)nny{22?z*hb?I{}BI};5(_k z<=7CP;BzYBO#JljZ`yb@1vnS@bzm|;c(#VyG`zsVZwAII9Fp=Kz!zxwA^i=&c-tvY zKjG_vKLyO~BR`)5#`{Z?`VU#~_bvDZ3qEGSPM6uz882<_b>eYHQO;`N;2If$@6VWc_;6 zg58*ae2)QF1AoDQF9QCe0rvva|GL%nHv`lE zxz+Jb;Qa=?8yIuIB>#Tk2Mzcez+VNX_Cx9Up#{HS!LM1cJKL;ZV8Kf*c(nybEO@5{ z@3r8EEcp8t{2L4Yvjx9p!EU^E!kGWlEV#&m%Pn}71@~C+WfuHt3*K$P`z`oe7EJH- zFsAo;3;u5l#(z^a$xpRldc%d$UYP|qTku*7j#}_`3#PYk812)$F^u?83x39e@$Uys z^7Iy+N3{A%{r?Q$-)i-la0&2pI!1e?7iav=fIEQk3TOU2G6nogfzQHx2(N;`djs*m z+JKh=Q-hcTe4~bW`vCr;1wRRlS1NOP(*F_g1={?I((`)_Q~M-52Ha}kPe;V7fUm+l zllZfN@zPrUt{TGU0_WhIPM)S;4g3)UZUtTftlMt~UJ6{J$*%{#68I_&ZvxK3IiE@m z4+CESOmEAf_^t!K23VKh4V;5>J_8#69^fm0zoX&(z*RW!vsuH3fS&~3q2V78AJ4-J zHGBkklL7x3ct0?`hlb*(1qu2e(OnvL18)NMY4{Z2-N1ege-!v>;OjJuH`%jQIBTTm zzY+NJ!1Q`Cvflzs>mldCVKiU482GQ^|IFc?c@i4{*8cAt$HTz*_}1c*gD3i1fDz{F z4LLXwy+_9ypA~faW8qLAUu`T%05WaKPb|Rq_r~eOc;SQnQLU z`;p?uqrD~rSll$>!8jI-LE)=m`Wv{1KuCXx>O?Q*Zfy%x)YCRNULuW`Tw~*m*4TPO zeZhE?)l>zVSxq<;~wbE9pHX{Q3sA#6!pMhXpoYs zQ*aC{+^44ylCx*e=IefD{`zoiAlyfW@R}2UMWnAU+>t0Kh$XNS6x&o#fFor5GYP+R z68@4&_<>3I6_fBQC*d!&x@A+`;5@v^1wNeMyLAz~yPOy)Hv>^oPVkpTH~MQ`JdIO_ zdg0s?_|$5{>QgHpc`}ummA_~bzSXBz{i^rYFDagczhDynIg{|uorG_#Q ztut2r>i5kX}YqN;=3?@1w8wZR{&kr*xW5IBL zG_lFh(0PB_hr_LgUV+ZIhWg%D1lG(WrU{8iuU-1PAEEscu4OXe{cYQ*xK~vhu;+ zzRo}*5$jzyh;7k=g0`B*AWl;$I!(dSSs9d{^O2>*_@XTUy)dE9xr+JQuL0p`fW1$9Jm=TAG?` z3#!Tkiwjm=RDiL4Wo4kHvZ1!Tprz`9#Rbh6!WS1*1x)ld!L!yhfRu<~CS|2}hcSPdm^y0I6J+~3g4oLL!8iJAq3f_-rVK;(VNdQO99 zkS>fL+fDxW8RLJ|shRN4bSC}}oeBRsC(VD%G5({R3I89*@^5i)RM_<2aBxVqBv=}( zZMi`I2S62pl_kNJi%KTYS}UrIw93XnNe~BK2JpmT5;ihSmW_-BCo;A0M2vGz#8`A9 z#<@lYoq8;`5=zd&nb8SEE5VcrvSUg-5lo3D!jhmVx#E`{1}E2+!tGTp#+U?YwS`nV zQ3@oJRP*XeqY|AmHpGO}&4E7ruP6)62wR(LO$7*S%5qzvvDuu~w%W#$V0lZu(F&)T zx$wfu6-Ln@4z;1HrH-Gk4A5!;^^52qzz8NbMuIr- zj*&3fAMTIDXn;o-!+TB~_{K@Af>OaZGKQiUG7JnJ1x~s0e;%esz&jZ&dYUXoan@AC z8Vg3lv1lyPL305sJ<)^Znoa`;({j;a1%tH(h^ZhR?(gkE?}y(5Xt@}O1P#Psd?WRy zMhfDI(J0!b9p@KIFST%r2$_!iCJ*QG9ui195T~E&rE`0!(|_hufvu*4e`!tzCQtwI zb9?E|@})n#H|g0xYF=r6>mh!E!EDLC`LLuHGu~WFMq5-rfhv4ls*h{R?HV`X^Y zA`<_6h~F&s^$x7p{w>`?`pF_*1dP+s>wWX*$1&IMNFads1NU`fs@H=s&5nbi&dwNS z%{1HYihzh9$#3dk7wL;5G!zSW;fC|n-NE=^l*ak^(j`k4lz`X~9bAeZFJi7bzi|O@ zUvE6I)W4wrmtZoVVuyw(25m~7h9BoCr}Qn258~Kp zY*QQ$0r7d_nusJqeerpN186y&^KhO#jDN)Evi`>5eZ2dsT)dVTWwQpoHr+ac8~uGJ z#ZuR$!Hw~gWUJ?2PZcuPF*LM>Zqexc@DO?{%%=z7$dhdQB%2GZ>;2a)YK7Z>@=9bw zSCpCtS^|og|I~v1i6s9IkmoV68XsY_8XsYNH9j(7HQq?!tMNtxt;QQMt;QQMt;QQM zt;QR%SdEV`eo8gDh)*Kcw{1tz^L&VYXTqmS0n0^oW8UiT)oY z-6!-+^8zJH&MCeSJZlHlg$`>a9yq}YMLXh4i{g>4L|4@3n_ufMO20QTPcVXQcuvPZ z>nxe~K7VbCu6&YrrJvXmHn3=d+SFLWS}sH&fPkOpHyB#CE*9RPqpnz}Kdb}lAoVat zf+QVJzujRhCJ6%=378+Dg@9z+G7UUj{f!#6wPu*~%?MWy0sn}Zl zuL~Uc*+zu-`yo5@#ZfK#@Vz&(rGID)qz{gk@Q85akUqYJ*gMBr+T=%%leWmnp8g@Z z3pL|J(|NNEVWMA)P0co(x6wbk9PRDtVdDM%RL1rh4kqh7v}Tjswb(>_lMXg%A6>2* zSPv6x$10pzr43W-ZJ!TpxgTT5Du?|A+ZJdA9KRRy<2*!B# M-6sB{h*j?Y0R>#(o&W#< literal 0 HcmV?d00001 diff --git a/Objects/example.build_log.htm b/Objects/example.build_log.htm new file mode 100644 index 0000000..1ae0388 --- /dev/null +++ b/Objects/example.build_log.htm @@ -0,0 +1,117 @@ + + +
+
Vision Build Log

+
Tool Versions:

+IDE-Version: Vision V5.42.0.0
+Copyright (C) 2025 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: gxyos gxyos, gxyos, LIC=DSNXV-PC3KH-IN3A7-EEI2N-RW7ZN-3M2AN
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Professional  Version: 5.42.0.0
+Toolchain Path:  C:\Users\gxyos\AppData\Local\Keil_v5\ARM\ARMCLANG\Bin
+C Compiler:      ArmClang.exe V6.23
+Assembler:       Armasm.exe V6.23
+Linker/Locator:  ArmLink.exe V6.23
+Library Manager: ArmAr.exe V6.23
+Hex Converter:   FromElf.exe V6.23
+CPU DLL:         SARMCM3.DLL V5.42.0.0
+Dialog DLL:      DCM.DLL V1.17.5.0
+Target DLL:      STLink\ST-LINKIII-KEIL_SWO.dll V3.3.0.0
+Dialog DLL:      TCM.DLL V1.56.6.0
+ 
+
Project:

+C:\Users\gxyos\Documents\ST30F103\Example\example.uvprojx
+Project File Date:  07/23/2025
+
+
Output:

+*** Using Compiler 'V6.23', folder: 'C:\Users\gxyos\AppData\Local\Keil_v5\ARM\ARMCLANG\Bin'
+Build target 'Target_1'
+compiling iic.c...
+linking...
+Program Size: Code=2758 RO-data=822 RW-data=0 ZI-data=2656  
+".\Objects\example.axf" - 0 Error(s), 0 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: ARM
+                https://www.keil.com/pack/ARM.CMSIS.6.1.0.pack
+                ARM::CMSIS@6.1.0
+                CMSIS (Common Microcontroller Software Interface Standard)
+   * Component: CORE Version: 6.1.0
+
+Package Vendor: Keil
+                https://www.keil.com/pack/Keil.STM32F1xx_DFP.2.4.1.pack
+                Keil::STM32F1xx_DFP@2.4.1
+                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
+   * Component: GPIO Version: 1.3
+   * Component: Startup Version: 1.0.0
+   * Component: Flash Version: 3.6.0
+   * Component: Framework Version: 3.6.0
+   * Component: GPIO Version: 3.6.0
+   * Component: I2C Version: 3.6.0
+   * Component: RCC Version: 3.6.0
+   * Component: SPI Version: 3.6.0
+   * Component: TIM Version: 3.6.0
+   * Component: USART Version: 3.6.0
+
+
Collection of Component include folders:

+  ./RTE/Device/STM32F103C8
+  ./RTE/_Target_1
+  C:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include
+  C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include
+  C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc
+  C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver
+
+
Collection of Component Files used:

+
+   * Component: ARM::CMSIS:CORE@6.1.0
+
+   * Component: Keil::Device:GPIO@1.3
+      Include file:  RTE_Driver/GPIO_STM32F10x.h
+      Source file:   RTE_Driver/GPIO_STM32F10x.c
+
+   * Component: Keil::Device:Startup@1.0.0
+      Source file:   Device/Source/system_stm32f10x.c
+      Source file:   Device/Source/ARM/startup_stm32f10x_md.s
+      Include file:  RTE_Driver/Config/RTE_Device.h
+      Source file:   Device/Source/ARM/STM32F1xx_OPT.s
+
+   * Component: Keil::Device:StdPeriph Drivers:Flash@3.6.0
+      Include file:  Device/StdPeriph_Driver/inc/stm32f10x_flash.h
+      Source file:   Device/StdPeriph_Driver/src/stm32f10x_flash.c
+
+   * Component: Keil::Device:StdPeriph Drivers:Framework@3.6.0
+      Include file:  Device/StdPeriph_Driver/templates/stm32f10x_it.h
+      Source file:   Device/StdPeriph_Driver/src/misc.c
+      Source file:   Device/StdPeriph_Driver/templates/stm32f10x_it.c
+      Source file:   Device/StdPeriph_Driver/templates/stm32f10x_conf.h
+      Include file:  Device/StdPeriph_Driver/inc/misc.h
+
+   * Component: Keil::Device:StdPeriph Drivers:GPIO@3.6.0
+      Source file:   Device/StdPeriph_Driver/src/stm32f10x_gpio.c
+      Include file:  Device/StdPeriph_Driver/inc/stm32f10x_gpio.h
+
+   * Component: Keil::Device:StdPeriph Drivers:I2C@3.6.0
+      Include file:  Device/StdPeriph_Driver/inc/stm32f10x_i2c.h
+      Source file:   Device/StdPeriph_Driver/src/stm32f10x_i2c.c
+
+   * Component: Keil::Device:StdPeriph Drivers:RCC@3.6.0
+      Include file:  Device/StdPeriph_Driver/inc/stm32f10x_rcc.h
+      Source file:   Device/StdPeriph_Driver/src/stm32f10x_rcc.c
+
+   * Component: Keil::Device:StdPeriph Drivers:SPI@3.6.0
+      Include file:  Device/StdPeriph_Driver/inc/stm32f10x_spi.h
+      Source file:   Device/StdPeriph_Driver/src/stm32f10x_spi.c
+
+   * Component: Keil::Device:StdPeriph Drivers:TIM@3.6.0
+      Include file:  Device/StdPeriph_Driver/inc/stm32f10x_tim.h
+      Source file:   Device/StdPeriph_Driver/src/stm32f10x_tim.c
+
+   * Component: Keil::Device:StdPeriph Drivers:USART@3.6.0
+      Include file:  Device/StdPeriph_Driver/inc/stm32f10x_usart.h
+      Source file:   Device/StdPeriph_Driver/src/stm32f10x_usart.c
+Build Time Elapsed:  00:00:00
+
+ + diff --git a/Objects/example.htm b/Objects/example.htm new file mode 100644 index 0000000..7ced7f8 --- /dev/null +++ b/Objects/example.htm @@ -0,0 +1,707 @@ + + +Static Call Graph - [.\Objects\example.axf] +
+

Static Call Graph for image .\Objects\example.axf

+

#<CALLGRAPH># ARM Linker, 6230001: Last Updated: Thu Jul 24 10:30:39 2025 +

+

Maximum Stack Usage = 136 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+__rt_entry_main ⇒ main ⇒ test ⇒ OLED_Init ⇒ OLED_Fill ⇒ OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +

+

+Functions with no stack information +

+ +

+

+Mutually Recursive functions +

  • NMI_Handler   ⇒   NMI_Handler
    +
  • HardFault_Handler   ⇒   HardFault_Handler
    +
  • MemManage_Handler   ⇒   MemManage_Handler
    +
  • BusFault_Handler   ⇒   BusFault_Handler
    +
  • UsageFault_Handler   ⇒   UsageFault_Handler
    +
  • SVC_Handler   ⇒   SVC_Handler
    +
  • DebugMon_Handler   ⇒   DebugMon_Handler
    +
  • PendSV_Handler   ⇒   PendSV_Handler
    +
  • SysTick_Handler   ⇒   SysTick_Handler
    +
  • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
    + +

    +

    +Function Pointers +

      +
    • ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • EXTI9_5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • SystemInit from system_stm32f10x.o(.text.SystemInit) referenced from startup_stm32f10x_md.o(.text) +
    • TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM1_UP_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • TIM4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET) +
    • __main from __main.o(!!!main) referenced from startup_stm32f10x_md.o(.text) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +

    [Calls]

    • >>   __rt_entry +
    • >>   __scatterload +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(.text) +
    +

    __scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +

    [Called By]

    • >>   __main +
    + +

    __scatterload_rt2 (Thumb, 84 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +

    [Calls]

    • >>   __rt_entry +
    + +

    __scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_loop (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, __scatter.o(!!handler_null), UNUSED) + +

    __scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +

    __rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +

    [Called By]

    • >>   __rt_entry_li +
    + +

    __rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +

    __rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +

    __rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +

    __rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +

    __rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000034)) + +

    __rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032)) + +

    __rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002)) + +

    __rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +

    __rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025)) + +

    __rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +

    __rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +

    __rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +

    __rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +

    __rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +

    __rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +

    __rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000006)) + +

    __rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000010)) + +

    __rt_lib_init_relocate_pie_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004)) + +

    __rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000035)) + +

    __rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +

    __rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000027)) + +

    __rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E)) + +

    __rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +

    [Called By]

    • >>   __rt_exit_ls +
    + +

    __rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)) + +

    __rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)) + +

    __rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +

    __rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)) + +

    __rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)) + +

    __rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)) + +

    __rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)) + +

    __rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000)) +

    [Called By]

    • >>   __main +
    • >>   __scatterload_rt2 +
    + +

    __rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +

    __rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_setup_stackheap +
    + +

    __rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +

    [Calls]

    • >>   __rt_lib_init +
    + +

    __rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +

    __rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +

    [Stack]

    • Max Depth = 136 + Unknown Stack Size +
    • Call Chain = __rt_entry_main ⇒ main ⇒ test ⇒ OLED_Init ⇒ OLED_Fill ⇒ OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   exit +
    • >>   main +
    + +

    __rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +

    __rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +

    [Called By]

    • >>   exit +
    + +

    __rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +

    [Calls]

    • >>   __rt_lib_shutdown +
    + +

    __rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +

    __rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +

    [Calls]

    • >>   _sys_exit +
    + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   HardFault_Handler +
    +
    [Called By]
    • >>   HardFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   MemManage_Handler +
    +
    [Called By]
    • >>   MemManage_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   BusFault_Handler +
    +
    [Called By]
    • >>   BusFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   UsageFault_Handler +
    +
    [Called By]
    • >>   UsageFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   SVC_Handler +
    +
    [Called By]
    • >>   SVC_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   DebugMon_Handler +
    +
    [Called By]
    • >>   DebugMon_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   PendSV_Handler +
    +
    [Called By]
    • >>   PendSV_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   SysTick_Handler +
    +
    [Called By]
    • >>   SysTick_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +

    [Calls]

    • >>   ADC1_2_IRQHandler +
    +
    [Called By]
    • >>   ADC1_2_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET) +
    +

    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(RESET) +
    +

    __user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f10x_md.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_perproc_libspace +
    • >>   __user_initial_stackheap +
    +
    [Called By]
    • >>   __rt_entry_sh +
    + +

    exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = exit +
    +
    [Calls]
    • >>   __rt_exit +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    __user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    _sys_exit (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text)) +

    [Called By]

    • >>   __rt_exit_exit +
    + +

    __I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __semihosting_library_function (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED) + +

    GPIO_Init (Thumb, 390 bytes, Stack size 32 bytes, stm32f10x_gpio.o(.text.GPIO_Init)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = GPIO_Init +
    +
    [Called By]
    • >>   IIC_GPIO_Init +
    • >>   main +
    + +

    GPIO_ReadInputDataBit (Thumb, 52 bytes, Stack size 8 bytes, stm32f10x_gpio.o(.text.GPIO_ReadInputDataBit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = GPIO_ReadInputDataBit +
    +
    [Called By]
    • >>   IIC_Wait_Ack +
    + +

    GPIO_ResetBits (Thumb, 20 bytes, Stack size 8 bytes, stm32f10x_gpio.o(.text.GPIO_ResetBits)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = GPIO_ResetBits +
    +
    [Called By]
    • >>   IIC_Wait_Ack +
    • >>   IIC_Send_Byte +
    • >>   IIC_Stop +
    • >>   IIC_Start +
    • >>   main +
    + +

    GPIO_SetBits (Thumb, 20 bytes, Stack size 8 bytes, stm32f10x_gpio.o(.text.GPIO_SetBits)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = GPIO_SetBits +
    +
    [Called By]
    • >>   IIC_Wait_Ack +
    • >>   IIC_Send_Byte +
    • >>   IIC_Stop +
    • >>   IIC_Start +
    • >>   IIC_GPIO_Init +
    + +

    IIC_Delay (Thumb, 2 bytes, Stack size 0 bytes, iic.o(.text.IIC_Delay)) +

    [Called By]

    • >>   IIC_Wait_Ack +
    • >>   IIC_Send_Byte +
    • >>   IIC_Stop +
    • >>   IIC_Start +
    + +

    IIC_GPIO_Init (Thumb, 72 bytes, Stack size 16 bytes, iic.o(.text.IIC_GPIO_Init)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = IIC_GPIO_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   GPIO_SetBits +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    +
    [Called By]
    • >>   test +
    + +

    IIC_Send_Byte (Thumb, 134 bytes, Stack size 24 bytes, iic.o(.text.IIC_Send_Byte)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = IIC_Send_Byte ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   IIC_Delay +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   OLED_WriteData +
    • >>   OLED_WriteCommand +
    + +

    IIC_Start (Thumb, 68 bytes, Stack size 24 bytes, iic.o(.text.IIC_Start)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = IIC_Start ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   IIC_Delay +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   OLED_WriteData +
    • >>   OLED_WriteCommand +
    + +

    IIC_Stop (Thumb, 54 bytes, Stack size 16 bytes, iic.o(.text.IIC_Stop)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   IIC_Delay +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   OLED_WriteData +
    • >>   OLED_WriteCommand +
    • >>   IIC_Wait_Ack +
    + +

    IIC_Wait_Ack (Thumb, 134 bytes, Stack size 16 bytes, iic.o(.text.IIC_Wait_Ack)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   GPIO_ReadInputDataBit +
    • >>   IIC_Stop +
    • >>   IIC_Delay +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   OLED_WriteData +
    • >>   OLED_WriteCommand +
    + +

    OLED_Fill (Thumb, 110 bytes, Stack size 16 bytes, iic.o(.text.OLED_Fill)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = OLED_Fill ⇒ OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   OLED_WriteData +
    • >>   OLED_WriteCommand +
    +
    [Called By]
    • >>   OLED_Init +
    + +

    OLED_Init (Thumb, 196 bytes, Stack size 24 bytes, iic.o(.text.OLED_Init)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = OLED_Init ⇒ OLED_Fill ⇒ OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   OLED_Fill +
    • >>   OLED_WriteCommand +
    • >>   delay_ms_simple +
    +
    [Called By]
    • >>   test +
    + +

    OLED_Refresh (Thumb, 124 bytes, Stack size 16 bytes, iic.o(.text.OLED_Refresh)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = OLED_Refresh ⇒ OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   OLED_WriteData +
    • >>   OLED_WriteCommand +
    +
    [Called By]
    • >>   test +
    + +

    OLED_ShowChar (Thumb, 132 bytes, Stack size 8 bytes, iic.o(.text.OLED_ShowChar)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = OLED_ShowChar +
    +
    [Called By]
    • >>   lcd_show_all_ascii_lowercase +
    + +

    OLED_WriteCommand (Thumb, 52 bytes, Stack size 16 bytes, iic.o(.text.OLED_WriteCommand)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = OLED_WriteCommand ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   IIC_Wait_Ack +
    • >>   IIC_Send_Byte +
    • >>   IIC_Stop +
    • >>   IIC_Start +
    +
    [Called By]
    • >>   OLED_Refresh +
    • >>   OLED_Init +
    • >>   OLED_Fill +
    + +

    OLED_WriteData (Thumb, 52 bytes, Stack size 16 bytes, iic.o(.text.OLED_WriteData)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   IIC_Wait_Ack +
    • >>   IIC_Send_Byte +
    • >>   IIC_Stop +
    • >>   IIC_Start +
    +
    [Called By]
    • >>   OLED_Refresh +
    • >>   OLED_Fill +
    + +

    RCC_APB2PeriphClockCmd (Thumb, 56 bytes, Stack size 8 bytes, stm32f10x_rcc.o(.text.RCC_APB2PeriphClockCmd)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = RCC_APB2PeriphClockCmd +
    +
    [Called By]
    • >>   IIC_GPIO_Init +
    • >>   main +
    + +

    SystemInit (Thumb, 102 bytes, Stack size 8 bytes, system_stm32f10x.o(.text.SystemInit)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72 +
    +
    [Calls]
    • >>   SetSysClock +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(.text) +
    +

    delay_ms_simple (Thumb, 32 bytes, Stack size 16 bytes, iic.o(.text.delay_ms_simple)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = delay_ms_simple ⇒ delay_us_simple +
    +
    [Calls]
    • >>   delay_us_simple +
    +
    [Called By]
    • >>   OLED_Init +
    + +

    delay_us_simple (Thumb, 46 bytes, Stack size 8 bytes, iic.o(.text.delay_us_simple)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = delay_us_simple +
    +
    [Called By]
    • >>   delay_ms_simple +
    + +

    lcd_show_all_ascii_lowercase (Thumb, 140 bytes, Stack size 24 bytes, iic.o(.text.lcd_show_all_ascii_lowercase)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = lcd_show_all_ascii_lowercase ⇒ OLED_ShowChar +
    +
    [Calls]
    • >>   OLED_ShowChar +
    +
    [Called By]
    • >>   test +
    + +

    main (Thumb, 72 bytes, Stack size 32 bytes, main.o(.text.main)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = main ⇒ test ⇒ OLED_Init ⇒ OLED_Fill ⇒ OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   test +
    • >>   GPIO_ResetBits +
    • >>   GPIO_Init +
    • >>   RCC_APB2PeriphClockCmd +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    test (Thumb, 22 bytes, Stack size 8 bytes, iic.o(.text.test)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = test ⇒ OLED_Init ⇒ OLED_Fill ⇒ OLED_WriteData ⇒ IIC_Wait_Ack ⇒ IIC_Stop ⇒ GPIO_SetBits +
    +
    [Calls]
    • >>   lcd_show_all_ascii_lowercase +
    • >>   OLED_Refresh +
    • >>   OLED_Init +
    • >>   IIC_GPIO_Init +
    +
    [Called By]
    • >>   main +
    +

    +

    +Local Symbols +

    +

    SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(.text.SetSysClock)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = SetSysClock ⇒ SetSysClockTo72 +
    +
    [Calls]
    • >>   SetSysClockTo72 +
    +
    [Called By]
    • >>   SystemInit +
    + +

    SetSysClockTo72 (Thumb, 290 bytes, Stack size 16 bytes, system_stm32f10x.o(.text.SetSysClockTo72)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SetSysClockTo72 +
    +
    [Called By]
    • >>   SetSysClock +
    +

    +

    +Undefined Global Symbols +

    diff --git a/Objects/example.lnp b/Objects/example.lnp new file mode 100644 index 0000000..12749fa --- /dev/null +++ b/Objects/example.lnp @@ -0,0 +1,18 @@ +--cpu Cortex-M3 +".\objects\main.o" +".\objects\iic.o" +".\objects\misc.o" +".\objects\stm32f10x_flash.o" +".\objects\stm32f10x_gpio.o" +".\objects\stm32f10x_i2c.o" +".\objects\stm32f10x_rcc.o" +".\objects\stm32f10x_spi.o" +".\objects\stm32f10x_tim.o" +".\objects\stm32f10x_usart.o" +".\objects\gpio_stm32f10x.o" +".\objects\startup_stm32f10x_md.o" +".\objects\system_stm32f10x.o" +--strict --scatter ".\Objects\example.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\example.map" -o .\Objects\example.axf \ No newline at end of file diff --git a/Objects/example.sct b/Objects/example.sct new file mode 100644 index 0000000..09aa1bd --- /dev/null +++ b/Objects/example.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00010000 { ; load region size_region + ER_IROM1 0x08000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00005000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/Objects/example_Target_1.dep b/Objects/example_Target_1.dep new file mode 100644 index 0000000..af37958 --- /dev/null +++ b/Objects/example_Target_1.dep @@ -0,0 +1,176 @@ +Dependencies for Project 'example', Target 'Target_1': (DO NOT MODIFY !) +CompilerVersion: 6230000::V6.23::ARMCLANG +F (.\APP\main.c)(0x6880A23D)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/main.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +I (DEV\iic.h)(0x6880A153) +F (.\DEV\iic.c)(0x68819ACD)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/iic.o -MMD) +I (DEV\iic.h)(0x6880A153) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/misc.c)(0x68802F45)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/misc.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_flash.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/stm32f10x_flash.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_gpio.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/stm32f10x_gpio.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_i2c.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/stm32f10x_i2c.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_rcc.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/stm32f10x_rcc.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_spi.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/stm32f10x_spi.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_tim.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/stm32f10x_tim.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_usart.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/stm32f10x_usart.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver/GPIO_STM32F10x.c)(0x5FC04FEA)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/gpio_stm32f10x.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\RTE_Driver\GPIO_STM32F10x.h)(0x5FC04FEA) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) +F (RTE/Device/STM32F103C8/RTE_Device.h)(0x5FC04FEA)() +F (RTE/Device/STM32F103C8/startup_stm32f10x_md.s)(0x61AD795E)(--target=arm-arm-none-eabi -mcpu=cortex-m3 -masm=auto -Wa,armasm,--diag_suppress=A1950W -c -gdwarf-4 -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -Wa,armasm,--pd,"__UVISION_VERSION SETA 542" -Wa,armasm,--pd,"STM32F10X_MD SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1" -o ./objects/startup_stm32f10x_md.o) +F (RTE/Device/STM32F103C8/stm32f10x_conf.h)(0x61AD795E)() +F (RTE/Device/STM32F103C8/system_stm32f10x.c)(0x61AD795E)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wall -Wextra -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./DEV -I./RTE/Device/STM32F103C8 -I./RTE/_Target_1 -IC:/Users/gxyos/AppData/Local/Arm/Packs/ARM/CMSIS/6.1.0/CMSIS/Core/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/Include -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/inc -IC:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/RTE_Driver -D__UVISION_VERSION="542" -DSTM32F10X_MD -D_RTE_ -o ./objects/system_stm32f10x.o -MMD) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h)(0x61AD795E) +I (RTE\_Target_1\RTE_Components.h)(0x68802E58) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h)(0x664BD888) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h)(0x61AD795E) +I (RTE\Device\STM32F103C8\stm32f10x_conf.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h)(0x61AD795E) +I (C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h)(0x61AD795E) diff --git a/Objects/gpio_stm32f10x.d b/Objects/gpio_stm32f10x.d new file mode 100644 index 0000000..ef71f6e --- /dev/null +++ b/Objects/gpio_stm32f10x.d @@ -0,0 +1,16 @@ +./objects/gpio_stm32f10x.o: \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\RTE_Driver\GPIO_STM32F10x.c \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\RTE_Driver\GPIO_STM32F10x.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h diff --git a/Objects/gpio_stm32f10x.o b/Objects/gpio_stm32f10x.o new file mode 100644 index 0000000000000000000000000000000000000000..1f274e54a2b4539dcd691ffbc8ff4f6213e5c004 GIT binary patch literal 9872 zcmb_i3v^V+d7gXc-qq@X9v}=DgeT}AR!bzGa6O)z@=N79PbGd>tu?V&Mk87h3 zUy+56U6JB+mMGi(>iBtWtm;=nd-;;4eWE)1d*kPWm*&ILHE(y-MMHSE-+N9eg3~L! zP;7-Fcxfgdg;3PmiWz)ZP^=)ujB!*!vBXx);A1ZoMNm}F6vume2fW+I&%6KJ5B*GI zw{AFg>*9^ZZe6_5*sY5<8oPDzMq{@w-e~OBG-Dq>uOA<%rKLe@X8&<9DqM4sW3K~& zbs$9d>C1b?!&kDz@HwU7JCLb4tu!6bOs<7YjVL5Pe`ITB@KdEU>q#@Q9y0yxRhrvv z%?y4{E6qY^Cf7u!A7N2E+2`D=!sf=$KZY9j9PRzugU5|gdGO&YxoDN+mt%!x#%tr} zNk32Aea;vg|Mj);vagSyH^#KZR3;xe!a7NqEA%pYy5u3v5?8fL#-TIaqoFg~i_cM= zEGs}AmBhtsm`5-!T_JRKgmNsaOrBLejC#(=G4Ea z!;_vPs@~ZLe}68hU#craou;CuKIaL~@x7<82#{zkJaGKjm3(mumniGT{y?SEm#Yi) z(Z{Y7Aie^jjbe{*)<)I_jM%+rXm}F2l_APXzCV7xWHId>-fl6fkHMRzU;LmhuIiV> z*l0+MY8hN1I5Fnk{)gv`-??3urH=|r8`b|>j9KsK+ue97-D^eKALP$5 zWq#qjh51EV+dLt3LyOMI&AlV{PTUMxCS-mIMr|xbVO?%6II}=R=Lq4s2_W;KGlj^S zqp2n+dS^iyokRR;sIylnbc3Y`gRSD2}Z&LLIN@+m5D3xYA!T{Y;oiaZfkmJo*-3G_HJOL829@qXr5jT^eE?gCu0`YvFfI8H$PerC zM}WohBJwA7DWE8obCG{em$w3z$hF9i=&}*8Q+6PKTbK6}c;sIKI^{FSf2PY92|V&& z0NwID^8e7KCINboq0DUuu}k`LADG44qGxpP%1Y8p0wmW1f}w$fX`X-Qv{{*FyM$Kzd}$dzX^EC zl4l7@*#N*=`vUG}mTrCwcfs=sWMiP^Rhd;H z-<95-F#Z#yyex%xw`05~4ex%(_;2a;KIj;~l6l^T9OKur(EBOJxFUAK5Tyy~^kYWErN3`{pS^_7m7LW?<`FYj}@3P1oUY^Q>d6Hw^DF$EY&A-Y+{w z(8%+?;270Lq4!&k5i*LsuQ*27nD6~($A}mu-XAzdjbVBJ%`s}Rk(iHDV9z02>P28# zMwW%g$@@!3qa(2Q977_o_hGyXIhDP|XhQ>*CVE^1L(QtkC=t0-%KHt3hL|N#lpjS=Tc6X3;!!GAnk32jIP8;TKZSxl zNrW_fN;E`D6poWZslI_!f3kn*4l9`Mv&ih}O{T5RRN9L4?MUw2ncQiu^i@<^t*KP+ z9abXU*U_8k@3KC;qBG#H^!xqWMCgw4w!vh2u)J&JzSLlOa9|*u7)q4ar#ce7gy+|rshavI2MdH+ElPci6%85G9=N)c(5^8-&AY2fLT-D6l{$)P7>5S9&XyqP9afD zTeIDyp(z}RM;n{lT3t5c3-}v0+&z`5xQ`tYJM6iaYsyP~nH#Ws%k%nNi zi*nh~icqFRQ7%baOEA`&DPl5HR*})2l2y0^P)y}?vPxSPZ$@{~V7(nL%T+(|8oE(x zWUbML%!m|a>!x^c@l)Doh6)`A>O>F^Omvo6Q*m9*6yKTSgYRia=i;ZdU!E~P&@FdQ zVkn3O6bu9?<4_b;y*l1py~d7B5n+G4In2Xo4*N6bOi`|Th<;XtHcZpIVqL;u7|SNo z8mo;q)@8&xrE0n+u}JMqO{i*WlZu&pnXH8;?bFM&%SUHVorF#NMv}zjBDz_*U31vu#$>=H`ZU|8H&|UzMXpd zhr}?l%8K}q2*oytXgDUCa8fnB##^FyN8+tpn^_n$)O3RWhgO}6!B`D7VOIAp8im(zq6-n zIGwbaV9iuwL?rtYJMaqcAMO(!(Au(4Q)7+jOYP)V^ad5_WS2;E#)mL5_TsT8zHjhe zu`AIl`Vs?aA$}icnqU=9NQq=(M~~1}q8O_1`PT@u0|QTv+}>9yJULknUXiWm3;ej% zi}kr;o;F`wpxvx3@|0?~X!wCGg0Tjn;h-xDaRQ^0=s1#rqpbF^{JdGj<8l%mX{+M}Ior?$(vED^g5pi0$m>2gD^-V>|7x(x~ z>5(sq7tDO>@|3FlmRtV~MZN5%PAcl}+|&z-`nH?;x}v`0rv6q@XWY~YMSWLM@&v-s zJh}4k#q0P*r)iUO^_tMkyqtQ3_#7JCCSRupJ~Pkr1gOs|>J2ybtfJ1ksb>`RuWssT zMg71{9aYp1-PBWxdQ(yIsXdR=jJ+jZH?=NLZe2#4zeJo_Iq!LV@)5Kul9zg{*t*St)!70Ri|S0H&h+}sSy0{#zw_(NrFCYR&$N78BRvPE z9n7N|4dxydi`_Px!YWs8P%QKuroQFB@9s2XHJ)MvYD$^Wd3dfKrklbo_s zlOEqOT}g_$E{p2%LDQ9_SSawaQs1X(@1Kp2hDX_^eSfy@5f|8|J%6^IEoOtKDWQFS zwrOl?*|EW@5(3O)xf6(1qJfsmH*u$SS(02TEd`fdtDHk9QDSF%~l}WTX$sq$^|eF|J@-%UI1AWo%;H#MsVA zADYQu590viF2?&A4=_H&c#x4kOH=zN7@uZ5#`smnlZ-DhewXo8#y1$>V*DxN1;)#a zR~a>|J?huXSipD_;|Ca*GJc4$f^iLF6=N-9BV!w5J0pEHr~d9?{0QSd#zz?chVfa( zuQ9&F_)m;)GG1o9%9w+#g!-AsxRf!#xQ=ln;}*swW14Xf<0l!9Fdk<-#rO*28;ox= zUSl-zZ0m@vfDmylV7!&Fk`UKjY;R=TOo)d*!FG!Ae#XCGJjD16Bb^_0>=&ol{tn~! z8Gpj~F5_<)y`~-C9L6P#c)V2nkST;~6)%ROkj}vrXE7t4cd7ppMrC8WQ#R(|HsWFX z3E{Mg?Jyzyw6ndP5PsA@@}ONGF4E7Xd4=xBgcOW#XL84IS3I#}M>@Gn_;AJ_626X9 zAAM^SOHsz@(w7(-O84v-9!d@hUpm>#ZPNG}N{sDca47Ar?CI}J*)};yj`ZvtQO>NKebdS(|ULR@KP!o7WaHz-EpMx~Sa~xZM5L!ymod zo#goYtgV~qw;LT&duLpZ?jSgKzpGvS((g>C-=Eq3Cfd_K4$?c&NshlCgK+z+fa9&z>q&`M}5-eq%i!w=@>w#F6JszwS^n83|c2Sx<(N0ez&9F z5p+iLSA@&ym(EX48x%zyCZmiBoSeDaN<1d6VwW0lwQX2kVqXBZF zI=bdEI=Top*a&L~9Nj)HJ5>+SM(j$YqqGSp literal 0 HcmV?d00001 diff --git a/Objects/iic.d b/Objects/iic.d new file mode 100644 index 0000000..b86df80 --- /dev/null +++ b/Objects/iic.d @@ -0,0 +1,14 @@ +./objects/iic.o: DEV\iic.c DEV\iic.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h diff --git a/Objects/iic.o b/Objects/iic.o new file mode 100644 index 0000000000000000000000000000000000000000..adff67aa4a931d113dfe5ac6b3e9aff1eeb9a3fd GIT binary patch literal 17576 zcmb_j4R~BtnLhX4xs%BxO_MZj(-PWgs3pX9lKvV>Z70nnWRkQEY096e(`hpK(fpB2 zXo{t&Z5NAcd5VG*1zT1`M8WEU>sHuhSA4{uRUTImfk(S8YgzFJuwq2l?)#p5&Ye5A z(RH841NVOC`+L9deCOPA@7$YCHMTVwh9Pt_M3u;LLWI^zjlD*aD$zsjKaXBXmUahE z8OP3_HICOWGH&nx!uhizBEXB|c~$oF=g+cd)QV$op8dsH^OWP|_#Jr6>sbZQZRc(p zJ^$N3p8pLj4?LmqX%~tZOQ_j)E;jn`bU;{wdtOr^XT|=sBjHdO>N2sy+ zvtTTv);#vLvwAc-pIea6eB@&tJ32kjt+S499Sjov$EL&g{G9E!UQIfsUu39|^Q8PsDw zcuHVZ1>Mm)Gf7;hZr(9nn9~tCwxBR-iE%HE-&X}+#8m))1Gssj@XX7ekvQXJ#5}>O zsb`bdD6b)nGt-E&D0+SR^EimLfE+Q7$q3Ip zgxh20T1u+Db?gg$WB)H-XHHn5pvbGLlItxfPSrm7MJEsJIEY#-F~#wt)3&UpEvBjp zq^-&h{@BKG_&~Vv=O-%{i!NjR>c&tDg&#t=FGj*hBzhHu32onmS-9f z@s|1Pk=I6r_?b}>dqapPaTsxUM~-xrHyr7l3!lHl_Bd>DcThXOUJu?CpI5a~&C#Ep z&!C*oATlp=Y>RbH;?;jC#yl3sx>#xNoc>hKaGspuJn;>8hM9x2nsJSyCN^r4CvH+T z35t-c$qJ0m7LmH6xZ5yWOJ-mRyDB0xfb`Xvkw1##|uh z`w94kYUvG$#4nJ&_f-Wjvnga=fXsm+@4_zvjkZr9QZc*=p);T{j(y$T{hgd-HCa)8 zoc-fj-jSW_!|4f;WG4^*iLxpDCze)ERhNoO=7f57i*<<|mF+^<7Hujj>v68Htbk=` zW2j7oa1II4UJG%EO^98)(2o>{0;bq_RibgD5SyoBIHj&iG>Ikkjjbz1d0FXHvADFc zvGH=Tp(T;16~+zuh_Eh^NURgVMB=hVLabW{9C0np_+P8Cv8FQ)SI^9`}FK9RUdOd-K3AWQ)*606^2KtkxL7@C+e z3(YAp6$lki!M+~I^bMka)slCkzu>Ya(S#@~u_UJOq_qi7o5bQsEV3B=I`q5CLS@|| zFEkp;6Buq|gJ3E`n81u6ZasnrOv4O_18hQAHbxie?ChKrQ_b;sov4e);}M>lr$im( zX(j($&PTU>F?jwtIey-eQ} zMv3vZqB*uzR6PHpq7q{Vo-fQb!YWG4*|cDN!4(B&IRG zY4$9c3=!&JUA$IWmqbO0Q5uYuJK;Ai5TZ1Sp=3puE}(FZElg#@jLX*Kuyb=!9G7_o z5=V&nen6H)i1HjK+i_ZuW2=M<-QYHZU*ratY(=gMp)bybrf89>1ctuYtwaGUA>M~V zVb?8nFc@7Gj_QC6Lx($c1G4B9K$OwIu zB+q;Zgdpbo6adYoYe=3Chn*G~>ve1Pr@(xWf?r!=_GdJ6&I-(aSTnz|LbJc1nK!M%*^g=F zw^s4&)0&yK%4YwQW`1Xti{f+0s)R$~d>A{QfzrISl!B-fJV(K8bIjWVFPZGozRbK` z{FvM^aza{1&@p!Yl-76A`ah_@E30po`ZuY+5B`CdssGe6ECewZhX4zIT-A7Nl>)8^ zV`mWsk4XVHVPj`G1y9P5w@ASf3ci7mvlAA3oZ@+5oH+4_6q1>KYm|`$wg^0i;4pU9 z(C-CW!*_lMeI*B%c@pU*iBt)LUK|h?OQbU%BqxJ+5^0*&FbZBxq_@an($Qi#jGZmC znPo_cGms8S<{P+BgjgeO-bKk0W1)F_-n$91#E>W+iy>O9kQOq<6&{OWiLs9sS7a@& zkQTBYyI^n;65LJfcRF&Wvdod&eUvvih${D|pfYyeLd+H?(<4%HjFKrvvEECsDd`2) z9Liyhkt{3ZIQB{Z6ZHR}F)s*i3Ku7crgcoGB|#2DW$gSMLGF}8 zl}X&GlL*QrT-Kgo5_cMVumTV$u%GO4ClDVQ@L)l?C1>|;6$lR(LVO5^vGX+J+-Ja~ zNXGd)BZyTDwot}#*@6QE{-lgEuMDmk91M7f@=qCDH}fhXYjfm6j_d&`hvZ@$Vjd1- z=MNb13r27yJnG;a=vfp9T)+6Y5Hob3ODx7tB(8@#kTe%xjDDJZlrVS_2nF=n82k#l zm$JJpZ!3r$$lD7N0s{XH8#{em>TYjylZXm%G%YnwY57%yz%O;fr0L5w`f@3wPQRzHr~}Y zxp!o|D?ZXaF$C=KuI-(xYnx!-)i{|N8XZiFrjg;yy2&~*F+4udH;fqF{i!iAF)*B| zOJ+neS>Mr7e_e8W;`+v9=XLFk$)woU))-G-*-^hm#1q@=H@7v4#;uZE*`C;z+&-F4 z_as-=ZfU+rcm%6_{MxL+mXV%xvOclZF_&CoYqF_rTYYC@>y=(}}7a5ZmdE zj5?k4a8Gjc-b`9@9qE*ZyCyY|N!EA2SE@AK%8s0{YsLmLX{@TD)NqeS5>I7P4%;*^ zIOz0bF48GJmfF)kFqu}0j&$!>dc5DU+TK61r-5r_u)8OTI_*iO1_zU=@$P|vCv_#FZg+a*5=q zh^YlV91&+Tg`sB#hSDPw8PPq|BSuqwY0*70h@0kK(vdOI-OmGK=mrsEBYTASYg~u* zF8w-qu#-d=Q zvCP0jxTx>gB8)tAiVaZ=avm*!EzQ_hR5%NKAr9TR(a}aXZg`uELe9-u2_uf|Hsb^4 z<{}u&+qBYgLxjDn^I~(8^xAT>bZw#V>Nr?e=ZnEj)YbX?xY4@0NG@iMpAR$U_48r= zxm>tmyYYOOe@@2@{!jUF(|2{q1+Z@8jbL+8Ag5NmDY*79_S*AC0bPzgZyK&W@XNsK z#v6&!iGd(*d>e2F#8-;n7tJE!?T~`p+XC+wxKq@~J4KDWQ`FRtj&e(=X&dQI4c6dJ zRMU>@XuPI1Juq0ay>rXzRZS}=CzJ7}_L^1EHPMwd@$`)Y-RYXdaQEN@uFt;`-1baQ zdwOhOv_Bai8@Mq&Rx>c%jZ4Bwu1hA@#gvjauI<8w!lR+Be(RN8y9b85qR}pxGo7yS zOb@n#Xg^2q+!?W)$1_8#SK+2P2{|4XTsGM^Ixqqmucm-$TVY|#Cj{$O!?5wnAHT*8 zJiII6Z4lbwHhWeuYTLcmulBdtvxC-0jHr~9MeY2kU2)LP@3rmVa@#0ag|`u2|GT7r zpY}fs|NNl!aihhyn`bb;PnsXHm;8-=NuOQWXWPF%c>;E=3f4Bk= z={wYVsMX`82lJ#hm|6V|sEfiU>@dbU7sKTk`+_ajqx%mAt$#C42d%%~-y5{PYn--= z`t1CZp(O}p+pYG+RtDz5UfT#3ShJ$O61)J|S%9@em3C3T2fZi=l+Z-0J?liU#a`56 zFF0-8vmYf5TK{F7R>*rDWXQr%+BL~C2nI)8K2F0|fn!m-6J4m#0;eX!Uql|k!P^K_qW^j(N`)Z}77v=e=Y4$V;C zyOh2a`We*sN%f(=*1lGI4u%(O3AWBOO%MNtc3**A2@0E!>Rp5~wb+%xemep#KN>`W zbNexYC@d=4Vpl*#E*~Ra{&tX0Ac0l(W!8->@F(Qd75Jy_n=+HW{{Fth{r!jf50jAd z{MSFjK>rB0{O}L#1&CMC%ji*@gSB9*5WX68DFg@Yh0oa+Bc)!5YcCLEF&*+v=B<`t zmxlYWh5)Qa+~*nbyned~s>O1|%dosEz%4&*SG3r(xUO35HOtk|SK8IqWOnHJ{-NK2 zP#gmh7Rxa#>$OXe=3EE>Rtj{cu|TGADY(Vps^72|x7c%J{CTJC@)rAI#;CEEEZ0?D z=^N8Y1S-Oqh#Lk>Q5#6qo)5pM_2Rx>M6w>Rq8M0|vyA=bB3Lbg^%5k)?WpyHU4kpf zdJe{mtcPHG5$CzauDT4Q*Lq=J)Gi2GpR=M^bSLbk)*j~MT&-dMxKAM+E41*_X!+`DmQT+o zrEIhC8Ynlud@bY}Sh%a^>b-Ya;+OmMxDk7rB`SP+`5W7{utdbCkGMK^EV0z5U+U9W z`Sevj{c@jvxldo~)7Sd+YkYb>4P~2!Hx{||smm(Sv&06UeuGaR^XX$gecY#y`}EB| zJ)c~&&BA+!-2B?IO7twe2+7sA`}9})`0IT9yL^1o$EW0*J}z-y2BoGY8qp!oXYx`r zC=Mw;BKdsr5-9Z?NvSzYJWEH__)K_4Goa+-G**p#4GxO{&MkE zHD0cyQnOan;4KdQ9exe|e8b`SY+Y*BiBc%3e@gNj#5GFKXXsKhCK})`8*od^9pW7- z9-pU6&A50-`5%^iv)G~R*8``->=byvEb;j~U23+8QBcO?GjyrhjE-yq z%X%R0wUl4syh|kxTXk8sKIPzrmVsuVBl3wx+!ejuV6lZw!iM_2mEy24M!hq0`y zjstK`Y4~z{{31nC(tnf6AH2*Tyo?WC#s@Fw8F{l+FZ?UvAehW|GcbW029@IkmGjjg z!-;Av8Z226UhTXupq?CJ(#aS-yJ*HZi$Y;Ca zuU9msDCdQKoDUOu-l6!9Df$^jKdNztDu`ii2zRP=X>a)KC5_sEF>PkI+A{u6qE2n z#s8i1nlR zC5lE#E1Zuov};iEc2evg*DF4)=nYDKv*K@6{GE!wpEM%GBZ~hLX(j$5O7Y)P^aVx# zThTX3ab5AjiFt%b!IvpMqWI;Czk(Fk7oV?a->zs<(P2ezR`ga<*x#x6Pm)#%@v!2* ztmxMjeNNGzkizblihoP-K|EJ5?p#t_uZtD`c171Ix>?b!iY66(kD@myI;kisAlEU% zNQ$K>*Rk9OAjFcA>lRBuQcSU2ub4tfBcxcTOBF@xa-Cu;krZ2pT&HUkts@2K21R3} zSdVcl_+Db`g+(Mi&X^O2170C}vJ z!-^guUFv)^BRxhQ^LU4%$4N2BdlWrMiut%-QKTkJJR~CpSx=ZsUe+U^#tnUpa_k4! zD!m*}NaYE=%oBAztn@OkLLp8nUdAgD;&H`4Ns78YulScpQP*>dpC&ECd~%-wei;_{T|6*KaHS8PcWLHx&PK zQq=Viisy}rb(MdN0K5wFsOwhh(Ui0?VsN45QQLq0YMV;h+iTc#i4|Ul_ih4Xi ziaIRi^^WoL_Xo#)j1=SjJSoQc15%9dJSoPNLM#*GIZj$B#OtI>vF>=?An&h{BHvEr z!aPNEEIk;-i{WT`a-e52icc?@sPk2BCQbI+8;o{O^d(cfcaNoS6w+@-Ect0mLP_W> z>x-HFmX|g5$hz@O4xeUc3_-K(=fPZepWGKze!i0*^0Ho8ne^r7!^H6DM20W?H{b85`I=fx$WnJGC0ahiFP1ZagzK<7i}j_p_lduUxrr zG)}qj5j5+RD{=x44EK)w>B#Z}XBI$ala=`*N^SP@r_ar!7#_)_qgQU-v0^;K5028% zhs9Lgud`XC3&k_|@%wGAiz}JIT7K@$HP4EC_Hu;!i*DBELb1xRyvrYyFhSN?}9lm!gHKYW-z|Qyj?Du;aYet*wH~nlr{;&Nr zdCPj|e4NkvU#RP7Xh_z#Z(ikm9BUXH>3(kmK5aXnwxYQ3GO67nI=**E(it|uETsJM zKT|A6v3q8`!6@g}d!R+)H+1uhtE>3)%RSiG6I} zvaL~66Trwe8)v_r*3m%s83J~r2Ps6W!-3nAn~Sz17T+SraIl@Z#Ifr}pEf+`w+S6@ z+!$nd{BxVeTkF`larwMMe?2a3w-Oz1+*dqt^I%Uq`tkYI8+Q`22oBve-d-QxYaTqt z(RkN6cy4~jp<^7{uxY#rG9J*<|k3itXs|6m{D#wAxBNuNk`riCvV3;3m*fib* z`d++#;OV;HG0Vl{?_O_ye9l})Ak{S9vygl7MuAra8|GJzgLcH{^CkXw=j{L(%4x%< z@%TLI#XAl>ogW_iT)g*Kx%nM|-z^f!IcdCJ*m?0z0#DZukB=^1vxDd6SByo#xU^x@ zcyS-z^Pc?h80zBjcP>(LuWLRh|BOJYX}ps@yfeV-hfOz*2oBmYkAn`Ln_mDt04Q z(T8`$lixCB$Nc#I!kgbcz>7hyo5uU55APW8YGKrkqY4M@i1$SY&&}^8l^<=`G~OdV zyeB>R@n?g^`yU6-o!^&%H`Dd;J0ITDz++72$KRM5?~E_M3MiO2ZP;{ve4pc;kJmi; z@qVN6oUNF?W^@%|AVFWxlpVlZKTtRwB1$6e@n=l5Fhl+%Wdc5EL($BS2o zNu?d}R^gx>`OECw{B}VxQ+{uQofj_#ycqn6M|+LO_buN1?tp@EG$!rXOds9>Pkx*~ zjknO54|jg=fnr!9I46xa&o>`OfER%Y^W$}*@%X#hn_nUFV1Be=(|Gu&gE`}U(39VK zWkwc zMrB9-DqsE10PhIox@o*EzWO}~ya5bz=}B3?5N+7a)dgXiWqndiu9!=~}}`|zrOM}OkAC_D1M zz&K#)uD=7o`w)2DG#=mIddFMq!E1xD&hK#t&&{t8K^TWNY#Q&&KD;^)-d1HtzxUwq z=7)cPC%=tAEStvb1?SB#2D}Jl-8kBD==`oiA9!wl%Ynx@v|-bDThRC7?E)U{h}WU) z$Zx^*!2GaWWm^N`dd)yW9ot5A9b(wB4TnK=Fm$yYK0Ug98q$vc=1Di*<$FBcr>?3H z|Edr%bkjP%_w$aUALGD3ww2?!2FAKBX&>IF@j!e^gMn(iln-y$a?}no*5x`6-nhc! zHO6)g9-2R(2M?ZjJU*?cw)+wOfm9=8x@o&!)RcYQF5yG2r)k|)=pf9fR?)6qGoadz z_fg%aIs?1qo_W(#6G6vYzf<@Ir^lOwpROOjUwH9OmJ2b2Yh5?3EB4{>4?7-&5$l)2 Yq4DJR2ki`6j2|w~s2D4iT`}nY0;IlOYXATM literal 0 HcmV?d00001 diff --git a/Objects/main.d b/Objects/main.d new file mode 100644 index 0000000..dac2c37 --- /dev/null +++ b/Objects/main.d @@ -0,0 +1,15 @@ +./objects/main.o: APP\main.c \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h \ + DEV\iic.h diff --git a/Objects/main.o b/Objects/main.o new file mode 100644 index 0000000000000000000000000000000000000000..22f2edc1027f9a48e1b9d4f05fa6ec9da2d7b5dd GIT binary patch literal 3536 zcmb_eU2Ggz6+Sa}cJ1ui>vilVPKl~5N>Nlbv-UcPT0E7>r=bSnB-m~{-pPnx-XqqNSibh9CQv`TD5t7*P5RTF~ywAM(gX@%uT}fxO zE82s1Z+&`KdujP5eMMaT)$MdzJb3x`{`BSBW0b!^^!5#n^ee{e9HqY`e##iO4?q2o zQ}S408`U04jm1PNeeiRsQEh*mNH?_7STZ@2{9=qq93_!DJVIm~f$~H$nIwws1c1a3 zP-#r05DhXg0zx#nV?&00W132q7)FlL7-xPI(a95G^pL6Xz_SzmETyqihlqxclfGjh zO35VnYGfx#l9SNSu?&NkL`GP^Au5K9Xj$SJp#CLvnl`G7=h!M_Q zB3s3)=ymZs^n#>oLA(n};&12-@e%r?;tu*VVi1Fli$mzs;$ifM#SHohivJAmuR#^F z#+LyDM*KIhxNJFPe2Xpmz+12k{u$ki;MyIr@38is>ml|f|5VMU_)rcMbXZ`0;e(XRrJI9)$}i!4V_0% z#%t(fMtl=+3r%mP4E^gPzlHib+y|$9KJXgrbwTk00{+D0iTF36e!%K7 z72I~$?bw}QCX@Ht8KzFl_A=|Pmzi(Z?Pk+%W=@*9>CBqzwq`Oluia?XIvbg9oLHZl zoSvMVJWu&brP{7J9kW4&nd&*;_WbHbZ`<{&MYpllMsmNpx;8zzfDfwky;{55vT3X1 zI~yG&Z*0~)DwbCBbLDxOUkc%LrL=6Vc5S<9O-(MI`8Guixjp>EZos13w5@z;sUIG) z(vr1MUe2$TmQF{lmEt|@T!bxe1=e!Z&4x-P5|LlHHvk;|odr3afVR+0=PW2{nf|8h z_3cw9VK1zd(aun*xI)WlbE_-p(8`6gEB&$7w!3!GUMDUsang;h<62I~3HtsD%)507 z)qcs;hoO_J5c6*ai$1R3M+dbD?T~iA_CWme+7~q3Xp~=BBy9jnTB9`JF2ulHqFqc44TDdhDdFQX zmm2($_MASK$`IMu)CN6{9=G^^Qo{@&xKl_g%w)r@nGLsQHs9?QYe6krb{n-;7JENi zsWqPRvuACmm0ew1oX#yw^?Fuup_0v+$IYp1(Z1j`>};viXlzGKq7rXD}*un3|4xEkYH!oGnI(`bS z>0bG7#9+|JcOw+(1z`;l*?D3^o1npnk8gN>Lv}?F?~Gj$G)mV&c^Is-NPT^izF+bO7!f}yIUf*?dt72!;)=v4C2mM;OY|l3Bgx-CE%8~2Ka_Y?;x&n{Nc^?L zHzmF!@h=kpF7YFYpGb_OKs?@<#EisgMy!iZ9sAEp=r^wPOwet_#Gny2M->?mLNYHgcV3I!`)nalMrg+j}1JXL5n)!{TTm!MWB z)8B40{=dTi!J;Sb8us-#Y)X`xgMoG4(=7e}xqY2`J{v4=pzV$0bErhc{Q?FIMYGZ| zgkzq8j(?-!d^nCzKJQiJ>wXW&auJQ~YR)R(W!R$m9zhVtaXxIJaDIyO{6sh!(Ix2v zgrf2t0pmC&&qMixB0%N)ZbWA{|8?ZQVoH?y9T=kXJC4az;Nuf4mKl|t;$lQZ`RcHtrd{RYxQZe`75835XZIDvskt&& z_4_OI=z1@Kq+#Rr@{O(5`$y<1H&l8H`J9MBsqerS&G%yv^?Q!Or}7QqgGjmP5!|!? NfS>blJjd}o{s&NKEb;&V literal 0 HcmV?d00001 diff --git a/Objects/misc.d b/Objects/misc.d new file mode 100644 index 0000000..ec69ade --- /dev/null +++ b/Objects/misc.d @@ -0,0 +1,15 @@ +./objects/misc.o: \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\src\misc.c \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h diff --git a/Objects/misc.o b/Objects/misc.o new file mode 100644 index 0000000000000000000000000000000000000000..558ea51bb4615754b15859dbb8b5bb3c6d31c029 GIT binary patch literal 6848 zcmcIoeQ;FO6~FhreVcuo&E^Xt@}UdzH5A|G3ri6(o81H!ldxt3RSYhh%}cU1`{C{e zLx%z)YOK(PmX1(HhSsV6(GI0!+wo&s@sFam)=@j1p?}y?+YYVMR>T=f)tU5n-n)16 zh&ZD&_GaGuo!>dyZyC`jC;28Q~CAeM*a7nQYTqJndFnz0XC@~IX(W&(^Kc+8-p)nBd5cs z-&bH)j+}na#W>W#r@4i#0;SfKQQuFv_g~fg{b^h_oYM|#*jqN*96ZUM^&t0jTgl_7*oFO}> zJ&&&C`Wu*;i!~f|bI(ZI1sC&d_ne#71T4*TZ<=3T%a{1;HPv5p%{+fC-+T>Yii=0< zD=XJj-mEdEE@!HLel=sR#Sqq2R#q~mHLz&C>W2e}yBdVCin0!!JoUU%v-|5+=oYOf zvKroA2ZdwhQmeCXl?7ECi5c@R1p6YKt0`q= zFZbxPB)Oma^tqDk<2Cwql03j?>5D*~z@zTxbM&yZJjfU8QAr-+%k>^f9_B0cxFi$2 zQNKfyM|i7#wc>H*%S=O9=^ILJ5XJ0$rA@6x{p@+P@`lgIQ2 zA^efZB;T$dgzyfLL%gIv2EiKkxA=tqILIZke48KeJ|!)OIa63AIr+kv!>S)c^1nco z`F;w}Xf>8WP}Wrk0iKE~D#>zD*tG0&$QrAnSeB1d-p1S&3Kpv#uMZGJO=GeA>Q=7* z4D3~C)qX4%4dE=2Z9JeqCoOmLy*kxpSrYt&_Z4Z`&KdW#ye)2vEySkO^Cuv)ODZ>`qLnneY z3i{sS+w$anhN9)kekKepbKeRtZ6jXupwz;%U0PGa58-KT(H7S5yp&h-hPR}=R%y5l znKEc?DyvwENR{Z1vxS0M(?&?sLv67QjLN2Ff05d9IG4%ivSzllCJ-uQ0z}iJW+50-)AAw|EHqTfo_j2`9plMN ze$-@R*4-FkGNDd^ndKN)OvHqSRx%5+A$BE@v@c&RX!5-Fm+w}(fP*{nG#>}4J+m}VwlO6RgN%uJ8?*uW>5!kIzV zIhIXP_vC22lq`wzX>c^>5p#%@GWooi1Y0%s-DeiM zbAyOw-e(8>*!UUyJU)VFO6K^DnHJ{uR&;xquJ{=) zKFTa*HoJz;;n(uH{5tm{zLevd#zMW_j8{OY;Wcz5rEKro_|iqOf;Js9mA4b zd8B;WLkx2i40p$)@!(BHlhG*TaIRnmrvv}rj>At|)7cbb#ZsoF8K?TVF+vkA z&hdWh9Pg))i5;u@F#+_1yFxwd`v=n5e#7WTZ<^BnVrdX(DthC42wTrgq%tjFSW|I~ z;~UG8Mi}nn%;jR5^^JuaG1r!OH)%Jx_i6s)8h2L)6>K~{?eQ)=eBNO#;5M}2My0TQ z6pFB+g)BwAdsw?33fNlUTn#Z`Xidivy;=JL*v*F4Fr;bjsJ6!aoTkEOZp&2+7)1As zK^)^;tM=YwgTcQSNT3oeZZ|gz1txAIw-F^VfDhi&uCld116e_y*DLgLKS~>Q=V>EOh;3hdxqWZ zuu^}0hFzaw_sy{TX4tD|*y*5}ZmNC7Dl1fG|Fb|UREA%rj;6AC4o3AYU?-rVDWEg0 zPElF2;B=nVDQ?zIhYw^r%jy)J{a4uO9IL}s^|yl48CIv*^{udPVr&I=Jhc^KT2^=j z_u}#g5#8~N1n5U!fenN>Z08ETh!6*Gqu_MDlm9IOHwfG$Fd;A_@T&qJ7I;|T_XM64 z_`JZE1^!;(+XCMe_>n*zlR|Yg2)sdHqrh7PZWQ=sf%tu5^}AQ#Zh?;qd{*FTfj-P7 z<(VsRnZQ0VC$UlBMi@F9VR1%6-PDS^KfSdT4E{R0AT6u3s(I+8z zTHqKV)_srQj|hBB;12{oE${_GY=&0^|DC`;3;Y)$_RW6;=ZH=9RSTR)i2bxg@Swnm zz)b@05;!cdC~&_(EUPshPz!0R(m1UB38e3Ts&kgWIfQVc&kbRK5OpjTXxZ^`uSM>iPpA`f)KoO@#1c#-KScHk?Qf z3>3^A%)kw(#EeufL%$f9Q7}ghe1RF}czST$G8)!J)w;$mh65RsrBWe1Fjg{)b_Y9R z0Y7|5W3ytZ;54SQLpf$-b0yPQ-?RC~VhKNbJ~^Abh&pf6S1avf_eF7EzMAjV?%S51 zUGHc*YdQ-aDkL*PakcrFahVt2;08ur!X?)z?#vK=hPDmshb1bv7&cM{I@zR%En=Ow zSX!&K3Y37Qx7v5{ran$T+H0~&zeyR@yB-hu z&_kT|u`@62*C+AFCgUxF!kL!{^_TTZzw4lL<~{4kOSf^EcP;um^LjuQ!!DbQ*KGTh z$GZ}o^2%>s>1ROi%zMs}mp(=^@B5J9TCTelME)xQYRixCA9!FY=PiLyULP6JWZu6) zcIN%NBQO2Vka=H%?996h#JLw_ykFRU<-DgvUfM_0q~EiUop~=f@NH%(?kJE1oi{AmAY|?KR6ePt9n$2b ziTtQO*`(h>2vR27Vfc+pC!n0l1#ohX_pD>Qbeogot(_6ihmAKdW4si;YDT=}IER)) bPxH3`kBn!+56e_;d2FcdB1f(8s{#HGtn?kA literal 0 HcmV?d00001 diff --git a/Objects/startup_stm32f10x_md.o b/Objects/startup_stm32f10x_md.o new file mode 100644 index 0000000000000000000000000000000000000000..cdbaff8a070784af114c2e1facb233e99c8f7845 GIT binary patch literal 6036 zcmd^DUu;`v6+gD~$LZQGY0GH3wlkgEwOwP!PSU2Kh1}Rq?Zs}5uk!~r==R3GNxb?W zzIL0SYAez<4OFCo5GrU71Hm*{g^I+(q)mcJMe4(lDm0;jHVKJJFA5pCqSYL4>o3u6DC z68pD<2&s~Hr`Shuq-gOw__Fw{sa>92J`s)^S4ssVtmZQ#(do$WNNhZ8HuXlcRoBdB zWhA;B8D7&W#gIv{TBTmA8r9}RKxtG0OiN{>5m>G@0*T6!Q7jt8z{yZ_B#^Jw$`b*- zQPIsx;NloUL`Q~)zd^By#aYv6n2RfG>os#RUMsXJh-WUU`H^A1`C?*Cuhh$il^?H+ z#hWusqp2nJY7w`yRDM>U&!pN)R%~NsQg0Ne^;UVypViyhlrbt9y{fMm?OCkGBO>oq z%XCg+Z9iLPO-yjwSig&H>RhZHiWPfU88?<%E16ogZDB3;g}hm#T2$xSde-e_y}EAZ zONGmA11s@GRsy2hV`V z=RfR!+CSjg<>|*$#>>lR5f~xExHcd@ly{-rQiE-V@lYV4`4mV!0{7r$u4Z{Gs4a=;Pue}268_09%1JR{m5Zs^9RG4&-^nN z{|h*OfBd)(A^so1`!I&9#oq^i!p46I&QDd^Z-V2<(&n#%)?Eflm4sV_{nSY zuY-Tl##7)p^0e)zz;WcUg!6mW#h-NX&v7HW|EDf~$Hm`u@gKPOx{F_O@e3|K;o`?! ze6Nf5y7=eV414~6ckw^DIKPAK{P+$?{@JG?4&(k zu3bC-*u_6|@!z=kPhI@`F8;EMS6uv}i%+}w2^Z(uw&#oGIXKPF$Iof0+}GrpXI7ok z(pfF0oR4U^g<-cTDNOkVmt|hRY|Pf3N+p*c>Ci+wG!eTdpURB7xFZJajtJlpZ8qzg z64COxb6V^|rb8c#b*QFtGY*}S$tH4kjhan4?g{S5IhS_?1y#!U&9;ZgIq#dDi`%WK zXe_EF<~mi5G~gBK^n%LaHJw(}q&-q%A)h*}jk#5hr_4T%$IJ@Hnpxpkw51r+B90Pa zr9%3Ek*1THN8pcWqEknhq)Eeug zX%)RxB_!W8DyeFz3C)~QXx190mZ%oD7)FTD&`R(r>18x*dg1b_q1Rzhav2TnSE$JS zh^8+sHH<5v$ktpOXI(=daJOO{jAxgD=;t?oeg~d>Q;a zI%o{_dciy!Hfzhx<$7SK77EvvUc?TYkM6x|fuU3={OGlw*feN)y|IEWIdUR45w@D_ zu+?OTm3lp{H}!D3R?y2~rBMlIvCC!{^%0I`)RY=N8H$94#Te-t;Z(IyZWWEkM^d;6 z(hYs7L>@jzcehtbJ==OSecl1jpl84DVAml}z>6DMhc`wKp8~r)JJDKE$Xqp>ji$at zA(%pXyT~Y1s8#s?0&o!y=6c0)Y#3!x(8~?IVvwV{A7AvLt$F2A71OqOsk&U-(HEAiU)qk6RZR?>fdDPs$|x zxJQyAhujC+D@`_gGS-tqg@dUKR`D^>IAb%XlireAbe( zVDn==`|*{)WyKZ``V#yC&`FW^9fv}W*>)X%52TaL#`|Q?uZTt7hK}>&zDMTA=R&!+ z7}6dr;vS6s81uz`j6qzorZA)j+tGvbMhKBP@tIPN*>nc~5J=h-a>(C8#H+Ip%PVNE U;+sS3Q~EL5?|T=1?>@rsKb>x?h5!Hn literal 0 HcmV?d00001 diff --git a/Objects/stm32f10x_flash.d b/Objects/stm32f10x_flash.d new file mode 100644 index 0000000..f459a1a --- /dev/null +++ b/Objects/stm32f10x_flash.d @@ -0,0 +1,15 @@ +./objects/stm32f10x_flash.o: \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\src\stm32f10x_flash.c \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h diff --git a/Objects/stm32f10x_flash.o b/Objects/stm32f10x_flash.o new file mode 100644 index 0000000000000000000000000000000000000000..4ca287bd0a668f05812c8bf8bb8c13f52697c7c7 GIT binary patch literal 20724 zcmcg!3w&HvnLqd5xi^zZnx<)s1q;sBQerKW^aZ83kY^uh+JrQ<1q)4@Oqyt3Or|td zR%2SUtAIgRD38*zP#5K4QFJR%TNEECuArd(sXytiLUqxlcD2M8-T(jGbMBnEohi6K z_57Ip?{~iMe6RDJbI;tl=%JWGEpTFO?j3frN5#HMpbutT7Q6V>QQx z_0)0Oigt@Ju~QsdB*d6?huB$KOFG(S?;BjoVbu5GeWrZ;SX4yY#2wM@(%NX7bsD+S zJaRS1Bhq%&@wb;gb$nBEv~Agm2TGqg@hYx-tG?YgFITE!sX8_So7p<@^G3d~eV;QH ziQh0@B$|F(89({j>nC}=3!g}N{JE1yYmWP)t(&6VRmW`Tc6QbrpJF3(c4-^?s?ev$ zTDNm_w7dGmpHrn((YBLErKWu&2jm3ET$(nuJtibUO#DkHkGj(L+;&FyF|q<9vI0a_fXL1=A`>#Q2%-o_BM?o2 zjOLF)GzG#|(XcK?zVP?3k(nc%gTGb2_QoF?_XM-%3fhVz??U#SJgVoIyj}Q2%G+cX zqj@V?*ADX<&ynAZrrE}PuzFsU`Q|vTpabx!>4dPJJaO{s=t$FVMYEp=-w(Gu_H3q3 zIr>#KTN97a&-{GU6zbCrW;9sqh~E)4$EOQaxe(nW1)@Ci0xD7VJ4b{>j&+1y{r*_L zw(Xnzy5laB@mAN~qO4e}j#-G%-s#+KMy6%o0$FFLT`9&6jK_os$z<|ded2W)bK#Lw z`}`}GWR-PXZ|?3$9OsR z7=H)j+T+Z5r_|o)K2>d{4~^S#=ETB|lfPy%b!H)77V>p|R+Pa`S$beR5ex8u&pu`Td>#3tqR&>yXJbE%W}h$OYM;zHFUdU;XDq#kdT(|Q)w=~((=yDHbw_4T z<9RE3#OxVE&&i|aSpAY)0P1zF_8tRb#Hq%;`fa>%5FFw`oUvhcv=lWA>opk5B05+3SHiJy7MgFOF6 zI9H-r)JaN+&nYC>EAhv&<~sjPbbiM!hXWjE3jRi%x8pBPT|WUMYPnL{o@hIBsnfX- ze=VVUC)v)$vbR?Dde=ds;3oXJ9<;s3iO#fda0(kh6tm+KjwtNZ#F!H)?9s$cPPFi9 zO?=WRE=+6UW~a1pizaSyrWC$k6aV5&E8M1uTb=2JAJxQdPF%z$fhwAgKkvcEsfw%u z6hw*=fKRjM(#Rd`vAxBFCHV7WeC&NrwAB8TQ}{U$kFw)_IQ>OUeA=-KAJ@cZ5W$n0 zc);-rzoCf-5zaH3c*uzrKBtL?5!(+m@mZ%t#F%Z5mWq)#F$W*(%9lY##wXx-*N^#( zj5C%J`zCQMsXvesD0v~`_*hrIM(N2`DFn7rU^40z3`3$6hs($;DRDa`X8976ASKR` zI?5?=k!AEOWX~$Ur%cK$Wlz7^)54xni)`^;DYKD1yR7}FMEFzuFs<#9)+XCG6+KRJ zx8w>r=qfqrLmafw(}TW3sf8Yc2nJm!x&EN_a?l+d^s>|isRF6`7lvwI>S0QqYg2U~ zb)F%CFtD{uLq{>#g@}aU&I{$7d?CZEu>S&>kJGG98)N!ZQ;Yb~KI^Xp}v!#w*hK_D{ zWL?=$9Zzc=#W)0$RC67RU`vjCTl*0$$s)aJS!85J7U@WX-!Tl@(%{EvaB@TiUNDD) zCP#kcd+EtRQzh4r^fNNjf90TcdXQJoLF*!%TTDP?Wfp0#$&g5%B~@PGtDFLDqC~1Z zK$VY07^&>#a<{I0fxTasy>dbLRe~EjYCEWst7zaCewD~ojVDMLdj@kCap_SvB_ghx zPDchAaT%l^Rht}eE(a`iS$rIHH3uz~gW$I#tt^*ZfA651)|D4=&@NgLa=6zZv9i#->pw6|_d`VdKWb#$AF#Ju_O)`5ZE#qsu3Uq^3y|EBnR7Iw|8oL^a4d8MdbT(M>-nHs9t zG`w|SsG@psu&zDbUeP$v(cW7DtrgAf9q${eSdr}MtytZFRiVY z*4EbzbZqW}|3m9nx6ZFz0-x5`54ZOX_9n&V{-K^t{qVn|yFDeAG*+)(wxMRt>dVz- zeM?JI%ZBEqS>)Q5W<}RFt!!?rZ>?8k>++TLO>0_3Oa1ElR>4o*^3~NfjrF2_m4xcr zmW;)o{mDqVi;tCQ)*_H?qpW2-W? zti89Zc56p(vbv)qIW$z;*QprIsbp6&-O*jMxvMLg%Ji@4?;YrPpAzzkn)d$p%~d^^ zan0nV$*NDa4<(!1Hzk$m>U4X0^N=Few)do$45S*{htf@h$y9r~XP{rP7{LZ?Zkb-i*R574S{YL{_IR!gSwYDyc_?YEkLS_D*oJH&l0a zrckY7$S|0yj2+nxm3sjG}>^AeR83AY3LM{@Z5zWKt76|9VkLc4@t3+*ZPRPh#Tnsugi zmUWId!vM;yqy#EKfLUHj-5b#32^PCXyLgRRL2za4!JWrTBGv_>Gm^80*#b)*` z^7UoOwdLsJ*)LotJe%a}`+f|kJ8=&p!LOu$ESW$6A=vS^I)n7|^ThF2Io~Yr@95p! znG79Z{#x2|ot^~t$n4`&Hl2CfNCqRop{x_zC`RK99ViP9XgEycdxCJ~A=(+YEVnqe$(?+k8}kz0TzA4YUbv-R zk6Qw?yrK#ldyADBaipO zZn4(|Vx{Zsc4PBg$17?Gh4qDErEaBE=6H=VRq-x&=BPU-;R@%ep}Sqjd7?N0jonb# z;H_|-4%eISC7gpp4d`*c3Z}EdjaBBd@UnDx6C93fhgZPi*FMmN330BEjP7c{b*l2U9|rNH(7h7-LAJ1 zVczxunW0xA%#i2Y@__^s_G+X-MZr{zA&M!U^S_bfn7MmUfln~aZd6X}b}%P-&dJE= zJ?>k#V=^B@+PX0p)WDe^e}9)d*>gVbj=BZAUAMw5nv33Je(%k)*K>aLe%SY%TiryS zS^8cf7r+X4;^S@sCia1AMyd3Ng}&SOUy~sDW00}#T$6mS%h}oOPU1X|SY5^(9p1_k zbRP6Z-PzmSGqC>72};S2(VgJE*PRMRQNn$jSLvRK*v{6=wE@u|aNXUW^W@e9Gx1d@ za-PUj&d+=F<8e4qu8WO18u5MDRxs+u_rQmSj1OLl`suKou)PJGusv>k zTSjG%nmW$w_aO#{_ra>W+jT1Pr2c7`C`Rt$aBD$>yR1P@@Yzl7bfjcr!ad8YK!zIJ zw_@St!eY<#ZSU|Xi|MD*x7}`Z8%CC)U`oBmz>lm20qg!Nt?}{?NyNv}w=1;*yR`*6n_qZ`c=N#U` z8gV`oz1uCQ@SGR6$TE32dbj6%4=ijlk08j*g82>3H-X+_GpL-0v~UV<%Lh;$MNP((UfK$kgHnx32n_Z_04cT z;fM3vH^|dtSfA5zqllv>oJ8oJ@O8y>yfEiwy{w;*%lcLwPpv;U`BI<7vdYrAcr5CLi|EwH2K9LzIpm5e`1I)9~K8X96SZh_K)A% zGR+ZFL;R^3CaxTOOUfQ^erqCsdWb(gG(H~U$3y&?A^yw|zdXb*5Ao-O_;W)1$`HRY z#GfDH&kyl04Dl}v@h=YXFAni94e|Y#Mzs*DCp*8{lp~gg_)GOriH=wi;;#ttSB3bi zLj21@{L4c8))1c$>od&}YeW3C878hAaYcxKMTn2*)mc4PW>Jo43-Q}R{EiUa6{5|j z>-48L#P7!nkl$J5?+azNBYuwG9QZvpj!&8GiAh+p8M;tB;P^D3mz3GX;tPuJ(-Xxr ziqDl+W|xT{E51)p6$_MpJ})V=r-^fvJfCNj+0(@Y7^6LUUS_w6uPB<&Ldxv8n1F9` zOG6vVHeveR7txv3cC~n#O!nY-;?N9o!KAH^j~H6&k&+P(VtTI1BD(Yg?cVf zh;A_(PO@&<&w3-Wo``I-XF(oF`uz%Je>wkxKU?7(g$ad~3R#qBvll3&GPK!9KBv%L z?B~&bm+uFW`LK~}rie5`5-3wqq3DGQxf7FLt&lF0UZs$EA>FAkt&nlB|6>YoQ+S`k zM-+Zp;kOkYR>=D0_~QzBU?6=4@=82gVY$Kzg_kO9RCu|u1M-<+mknglm@4qQL zNW^-0TG8KE_@4@YO^gV^cStynvc!o*B>hZ9&r~>}N6!s`{@PMj{py^8*v!h^(fkXJ>pbc{Sk#X6S1G{QuKog z4=DVm!sivfs1VCmt_`G5B9?$$Hz;+9C~3J~P?{1^a&nzaR~RQ^oy=6oEs^U4DU!%7 zkn04YNQ8@Wogf7gtB6<^bqbdeVXRSMGZFRQs&E|~S#I*`Xh^Wi$3U?3@%=HS#h_i&aMd3~&g1k%N9wO@FK85!a5&VM+_YqMak1E_x ztQ6u2g@=f!gQpaJlej>LXB0k5#C$)m@Gxli=sF_i zyj9Wbh*6a{jPE9mc}y$*FtJ$W1^gYPF^{(>{!U`4f1jlNM@eHIrQe{X-&2J6g_8dj z5%b9RF)1G{aw2F%G{JeLWHLc%P#0Ct@BCDf%fQ z=J6+rK0+)P0xxMxfBrR#uT}I2aS`%IySV-tF@pC~*^hZTj~K;$orrmP4-xZ`CSo3LAR_-iAtLXWa9>8g zuOlMQ-y$NvbD)!X{W%f&d^`6cort{LLqt9v zCn67jAR_)b_$tr1KTkxw&l3^nI{3`^L?V^!P2fkJL~^*Nb2xz?h0}>sUJXffCO2;0 zw4r_D##HheA%#SuW1x>O*@&6x(gQ(lUAGlPtG6;A7p z`F=uvLHW)}=KTp3qLIN<1(@jebUM|uaWmgFk-Gidrtkul?#VeF`VANV{RBBOY$|vs z<_&y?objGaK2@fO@8eK9WxCwc-!*WWX+33zd|AWkJQBIX&-sGPDZb~I%Bj_OJ1FyF zP*`bxp*PYgQ~0J7=aS5+UA=CVe}?4?SBZYSw3Jx7YR&n0mjo|hO-Q}m6V5<> zp`1PjFA3#0n|Vnnzs#vGF`ZU6|BFp>m|w!ZJ^e|uhP&|Mmg>kEid=PEa;Fq;h?8@) z`DU1O!YKYzc&F14yh)ZvOEy2JrqIh&e1R{2Iw zU|sV&(|XXlX?^=4Wa=x0KApcfgtfj~e0_m`!^%I(uxWi`A$@VfzZpu7{uW@o=^wv? zRV*^H%rNJ+|{A^{WO%VV82<710j=**Utf@yMW8o=ubbAlFQo5&=+o7V}9TKmUm ztfqg@8vfxCP@wOtSchg^y$j>I*`b=&cMx)>zQfR04jIlbe-YRI-R$cN{JRf_8~Uez zHP`w+5z@yWe<(+N)rLO)24VX5AfMsn@UJhVFA9CS{%Q?<^&$WE!6@xghE4m&XH#ap zal^lQCC71RVSwr1esprJ>ZbMa-~E~T%Arr!-%`hs=2 z9fR~4k*2l2&-rqJ-7#f%6@}2W+{3sq?JhIyHYqvU9mdCucP9qr+9&&cxxnr-%C3HU zLfhpT$+X*S*lhuiaOKE}&DnRa(VU$@dl(E1vDxxlU{^7D12lGSocK$~_4 z4ZA#_P>yyBVAQl5g}z*N{|s5k1$GCO-8S^IX}iD2wP|7OZ;s2z;{Z=a&wq6S98^J;22!!Y`_b9Ee7ISI1BgW6e?<>e3_2~O=DX#wyD+j&7 literal 0 HcmV?d00001 diff --git a/Objects/stm32f10x_gpio.d b/Objects/stm32f10x_gpio.d new file mode 100644 index 0000000..b0761cc --- /dev/null +++ b/Objects/stm32f10x_gpio.d @@ -0,0 +1,15 @@ +./objects/stm32f10x_gpio.o: \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\src\stm32f10x_gpio.c \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h diff --git a/Objects/stm32f10x_gpio.o b/Objects/stm32f10x_gpio.o new file mode 100644 index 0000000000000000000000000000000000000000..1a7d78f3c58f5a394813f9f0f4558bd124220719 GIT binary patch literal 14432 zcmcIq3vgW3c|P~vy{na0mSjn`g)wIRh!KjtE6K8B2r+si$+E3Tf)FAqucXx@)~nLW z5ru$k^N=lRd;K6G1MbG>00LKj06iv>!EbDJf{u8>eH8o{0V=JagFOh&5m zZDD->b;Fph&ie8EnLs2sW2~D$`|f-&B_xi`NtvnznNY-5GPaWGgiO`zUORb_fRYI) znPx}EVJe3hs$(TxJlOyA?GZitEjG<%-AXDwe6Gp%GzBx52l$20X z^Jl#OLbFqkGd;}P)He^!8taUsp?YRQTQ!x0Bg5Fk{Ui${8^eOr4$-ujUF{ z)=mdSaqy?}XM(ANlXfapW6!WICPneCXXejjq(nb-kc0U%Rw|?TBhLbl8IkEq6WU_h zJQk`9%mh;AvFYj(^uS6@33J9gmJ10nBaRuV=^A6k24B2myk@|@A-xtC2PrKrWgKgW zhvyhoLt1Mnu6u5!j8bdni8Dqj<5*~)jBk4Ot*P5ue!&PU(;}>9gemb_$XGneEq_py zAt|k`F;aSGq<)T$)`|7+WvmT|H8eYVjhxVO%nr^nD|_Fb9}P{3V`gM}R2&OLo*Xrl z6vq{#I`h?YW}b-Ld(IF>YO4QnP@(Do#>0?p)||teKXV)srbk!WhsM;`wMAzh_-&s4 zgKeH((k7x4#<5V`8;ADi@ER87p?49+U;MTCGulRAPHW7cS=!!{`@FovvnKKt%){y_ z6*G^cCNR&CXU@tvXhC!+Gc`3JW}K_#$=jjXd(UNvd#M|N<~r^pp?=!f`}WjW9_I4# za~Tnls(cCKf_f13Jn18p7Ry1{vBYuw*1$$&U1(qWINUjF&)j>i0ABQJJbrGK5NZvs ziNLSminHeeZhiiYojU!7g%}<`S12s3Ch=xv-t1eImu6#j8mY*uqx+1RfQp$^Xy1mp zxzt@Ri{Y z+d^2y!pd2bD@0%;Dm%mBun@K@03w(x8ViKTSP8Il9Hmf!q4hJDL9MZX?K>cywM|Ng zU1_vs8}KK@vUOm62y_lTg~K~h&5a_y{9t8~v>d+dqN^_wBF`44YM|cosJKujzamYh zAkB{L*eP`F*tE04FVk2+Z!29(Qfigz8iFfwyB22G#9EA5K<;V*?pPvQ)JjT-uPG#$ zSK(q9%T4RoB(2v-ioh=bA;XqT^9t)6TdhpkF|CVmwS;2TTO~AZ?Z7o)?ZLI!>cF+Z z`XsJ}*3G!)S@+<&#<~yJBCWXJItfx(-@?@pL57sUQc+JXu0>oN2ykUvV zXEpJr707%}6K`3e%sEZGZDnV^poz0qUgobgan35td_@z#wTeX622kNBErfLYcK7=+v+SMVWiFSTL|gWK(+?GZ7FurQn1zf^5pT2A4Q!!!R-Bkx$UZjXh`y z?9VfguK62_wUcBm=Vdj1#*L%o-!B#JlnPU9IO!^!qyng-uTuTwV^~)C=F!4jOqRey zj1W}b#a=3Vla~r@@lt^@Qm2%j*x^zFlNiG;L;7<@kZBZ}M}>5nY0#@!K?&YU8aIA{ z5=91k45@(ZS&_j=L7I;<(jsFUxGT-0MkSrBmcovW9BE^gHcF)wJxLp-(uUX5_b7FB zx~HqtJzbsdspui9ih?0j2$tuuqSvO7E%Aig8m6t{}WU=;c+Opf*Utb;S?1@ zGQFp?LQoFTDXD-V65Z7Qn!#z|IINTbZ>Rp#)X(Un#M62lf}dI-sV`^Mk39M-rT%W} zKTmz@PAWWatZ=*Zj+BT~VxtL(!Urg^(PRuD3#7tElM3*VEhF3{xgbMdp|DFjv)U!a zsRgdnop$MLg3k8QnbVzprkcP`cO249N0)Tw=;urQBh;UuzIcQlCLD?2X{?U$4{>=H z0%p&ufO$g^6U+r*c8H>XM*U5&%}%rESE$dk-erk!4b1)+4d%}9pP>2*t9!$rNA;ty zZw_Z{LiIDKV#i0#*;0tyI#{@4uyEb7aCNe9g|YZ)PFxm^oR=(`=Com{lviY4AqR`4 z-2uUT=u$H>G&(Yz7*1XpsTv!KkQ^9Hj754!#v*k?U5TEaL{DUUw0vu%ePm?t%1C@{ zsCzIz+!y)8w%)SRt)-=QiPlQ)fw$Erq0Yvajyta+q6J{W`5SWCQn z|9EUyVqh@V*1mgdd41XBWM^%CORPLv5iN_=CJqdACt_{Mo|eSez-WJG?byJ9#8_;6 zth-}8IkdGLo+dl{Mh8Zs-Eh_+opnfO9knCf6GI4pyrZpsYiT_~>ZqHH4~-5c#KiFU zK;JOJ@9vL}iQ2}ts_N!CQMX6JH7$*MJKIJRiJs1~(%lVzCOi%0K6=}N!0wTrL}yjw z9!FeKje9!loA*|=H}1K{+uBl_MqTTn_D&=__j=iEXle0CRMn>ofCj&MAlcbk*H+gq zYs8w?=7nw!3@60|E?dhxli)On#@be~7r*MZR$TCFuG!VkuB&MkyQ^ASMcwu7ji`5aR<*WPeY~@+@rJt2_K&yJb#@BI)OuZAZK;$j z7ghDht?OZjJ;$O3!Jv(*hF`7fo@I2dm4vFCz6~|=)a?%*1FJyG%hB& z(Cmn|C6cf-uJy*f<$Ye5}oEYbvye>XS zsOnA*j0}qw%qX@%Lq&>)wvmakZYPpXJFO0j) z>YU}#2=^3@_A^Z`=^V=a0{1uS)bEg|eh1I`&I8*zunPFA zX|CFHO-I+ja7Q%Sf#8`O9PK?gWnd9EPCkp>7$6K%K-lum$@(8W$z^1HGI+l=b6c-% z2d&pd?_t~8WoO6GcDK`Z*4uWc({|q5cF<`%Xn1tb-zx3h>1{jfwB4=RGRxrORkURU zttQQHWHt-mrJ#iOW!r%oN~{f1#%S$&V$MtGNxbrP)XtiyIB7`3-X z?dqtV9gNu*gIW{ZX6FNUMD5%ry8x}3pfaNN+TdMw4AtdP+Y0vC`DJ#nI zgBRRoXQ6sg)V8DcIxyA-o9u8D{8D=p80AsBG-~HZ?Jx{qga+_(A+{3LWl{Swh;4)h zd=x?;53PmZZU9E2c3zXcOq!IkTTm@=tgnnB$e5j5F8h-UAK+~P4<-=`dZvZ$rKgqQ{JXe5p|$D(RJfiFOU%QH&Vivt zRG)`xEbEh4g!eDTelWn0ACQaY15vvoY6pWALF*?sKZ>PmJrwB0&LUS<(E9PsT+Y_l zRa;JQw_OHaxJj;Fb~uE{3fP|}Xx(n-{kv@)#?ER-zGGhkb{1wck_>|g7o6o~_G(CP z>9totp()rGv>v_relGKW2}B{Ehr!_{v$@wUqyRG5XVb-ZklI6_xPez}id?&ELs@wfT-JAC{d zKK_S&^iCgL>7#3XbiEiv3#TBT6Y@<Gd>;6+;&bHk%?$Ccisth{z8Mzm5%u|O zkdNmUzT6^RA?fAfGq6XRGY?NRA}fu*O7x}iSBpCopEE7ryhL=R(Gl??+G&p?k#BAg zKfrw)X-9sOs8=-a`}57q#T!b$Qqr46hVsYz{d_Yf)+%}4>*t&0Vo1^LlHMjhr)b{e z=bJlZKeOO`BWPl!!Ulys3Yk~(rxng9JgM+uh0iE_R^i(U-&F_@C5RzQ(Tsz3SxR^> zOT^1ii6Mm)Mk&cwsFr<+dcZ585tI@pjmTsW)q`V+TBao&RJN~G7*V)hA(BAXCYBXl znZ?MFLYg#7oL7=;r;2%*5T%O0UExO*HY;pZc)h|tg+mI*72c%qHidU6yj$T>g(nnp z9y5+_Dg2&7=AZ4qRQQs@vkLjyjr`>bixtKcUa7E3VY5PhKcn7&!UGBqE1XeyT;U@M zf1r>bv`mcqe<=D_3V%byxc^qsd_poY2w6n~A$k-&qVQIQ_bU7Xaib6qD*BYde^U62!sisesPMN61DJb^D_7xa zg;+jv{vv#dAtDI5PXM_Uao%zZB692DyyKQbj1V#35Sm1|kn?J@Lb;D%K2?wg?jXV_ z_kCg|5%Z;1VFMA){Da32xl+@r9ch~NeljuJ6$NrjWdh!D3Z zoFXFsw=0|`qBHj>gbRV=$>}fFN`<0#5CbYc@MV0+kBkGfj3XrQXJd}O^oKl2yWr2T zJzIzqivJ)H`FU8;-zFkIPb&H;BJ%W{qUVT(_(Kszzez-%HqlS|ak)uITHD5%fdRgGA)%7DZ1Hk*9}<$cx;kkdFz}IZtjvo%7>wiRian zC+KfB=Og<0Q6l;`N<_atOGJMjCZZoN5fOhjY%%Tx5%HcNBF^s;5nl?o+KlT(BH|Iz zoaA5smA zO&)Jf@FA+Trlzy1rMlet#@d>|2-cwaf;X>G3`8>CC8Fau4M|*T(WFnVrN<_1W?_l` zzNNWxze>gESciQI z^#=Uto^sgQL_K~`A3X$QX#l}?9ip~ZjW(~nr(lnAw1;iZwRZw_m~i{i0s>o~TeQ9V z(BifC6WGI6D(zt#bnV@OI!w6naSx|o%CKmAJfpn!UVuFvAKP_*zmGahxbY=H=s#gV zvup2BN6z(o-gNBgw;tN>w;<>B`?AL`jtbZBX2+iEH-H4=C~%9mx89L+{YD_ie&D!~ zMa$v%Nb~!q$1mp+<*3JJ2mE*a7Q>!*ZfScTaO7OSyeFov#M7?nl)y&3IZzX2qQ@zF2;Dopp6_YPjaw?J>P z{=Nep$hm%Jm0$fa;{%Kn=pU+EtvNEr;zjdUE}e~Ij8f?XHNWg=he$g z_-*z1r2+bl;K!o<@-IQXem8pju2XWB041Ddk(&zVj zFs_mooQt-%-RJi&!JyyEm8_O4_xZibZ@Zh<`IsK;k`uiqEIz^$}fw7s+Fhu80UFsQHJifXwxAm{bl?D1O) zdCF0*$g$_ns{jr)?h(3Zd;C*huU{%qzg!7wIld$D`fd04-3nRlx6kJ{1bgk;sgfgk zqt9=L@~hwCYQG=%`R(xd-LC90-p}~__P`$ZZ(X##JA8g8mERpoP|F?k`R(!ey#lhj zzZ_fsbeV!Z?|XaA`yMK~PT3#gz+VqpT{Q2zsCe@{2){*e)&N1S6YclQK6|g=k5^LK z7*N~$lF#1ln}mp^-dPaSpNEfzAF$IvJp8k3XJGL@n2jKliNzt&5i9J2=*L zIVS%sSW^qU&q4@GWK?q~*P;oaw(;N2xVfB{A$N~vqE(0byl>nd#O4!$9Q#|VP&5Kdmmc8_p#nu>C^V=BkkPipk=C+`@U;` zYoB#CIRo4~bJyd^yT0}Pu5W#N?S1xH___LZD+7UmGA*DMsWhe3Q`MT|EYYw??F4t^ zoBJk0W1;c-cUAR^@2bFPP2Nw=y}99xDhiGT=AHZfN9Tg$N@MKQhBG57Afo{pJ@;mK zV&u5%k-kR0`S3*ESnQyR2gaU0yHGuSc7Y1VpFTTZRllp^C*J*(${EWW9~mX@I6m>o z+aR-01&`8KU_5*%=U~pE#`pJjy!h^%$|D~H=k3pjjiTdc7sMf7G`$wmpcWS8J$7&; z@3HBl^Ckm<=_9le8&^H6-#y%Z;@tq|an-Bm-pm<~9m?%lqb5FhXOb}-$0xKX{BuOD zV>UT%Wqj#x8Dn2@*9^=e^GNK@>4z0!qYhN|GCor*nReG)On+S{@I2$T@ z;%rEj|LwUq172*-DfZ(!&U0@DMT_-uzRu_pLiUf_~b{Z5v7<>HThA1W2{V< zi~Q`lKrZ*QHb(d8T<&N7NB2zaJ9EvdP)}yf*gs$A>9fJ217`#AC(Z`cGOYFSv%xsm ztEhH#By!47W1!C0H8p~oxX+GX*WI{!@WeN!uB!v^@xY47WGx?3v8mTG zv)+m&S-4N$QP0gzLO&bg#Z19;(v)OuYvtoUt(O zR-rN6@3@;OXME(r;FvS69>TqDT!jOuA4E_apZr`E@08&~(W=p!FxNXy`Oqn)(XGRX zwb${^s^YY(pf~bh0Dsj(x&p(Bw#8}?9>SL1{S)D_5MnxTHV^k(H5NwwLbH(iZWMv> zIIcl8KBHWX@#-s3@H9RP6h~E0=uosK%nWE7ZiIP?5#}i;qxN~71mKJD&^DtxQ5!ro zdSB)>!np)>OgTzlQIn_IF{e@W_H^h3wQf+)G6>%}@U3)=j37sHl%pfaQTALf)_-7n z;7QLtl$sDE z1Xth>9*%;cw@8L2NviN`fM`INGlHStYvvy{Q$`DeA%})TdH5SpP73|V2>u);9S`R$ z2;_&Og&?+bpdhTGe~Qj9iNbI&y3}xr!r|z0!*PNV{`H#wJo%s& zT~F!fS7Ys`1rIJfLh1wq1GV6&P0jxXsTYJd_ZX>vU=WauewWnuz5*+%fQ}RR1UCOK z`n)bsh-+NCxh_CIuEh0P;yp@KQzERxstzzNkf9rR{Z$9v@hSX~3U{Uz?#xuU^E`!U z5DGie3Oh0tcATehH5K-!74~N;>_1PTf(l2{3P&;(j-01ZLxp2$g=3it$1H^^ouy4w zIGI*B=_#yamQDr^AuC15vR=NQ2DnCcmiwuHI<0@&)7M!(Z8>z8We*iXL2p??!Hi`I z1=GvI?|p&Ik5VC?R)`yg;CeBZ}3uuRNOMiyeKSKTGY5nC!KXg0wmj^jRH60&4 zufXQ7Q(>hZhFPVHXQfthC$4v?&CgS6Q`+n%&#X?|CZiwxGkS4J*UNkz)=#PbX%l=@ zd-=4nk<&w^Piq@Y{xHeU1bK1V$^R8?98AY>(CE7*e$dKAxps<&KNb2`TH#wpA-J0! zzNN!)J-7;mc&-n9oRWqu_>g`n-^qP$3rb>LC`AdI%n( zhgis8aSc?MpH`S}6kHGUL%M*h_51`CmW8;?-g++6N_H;0DYYtXc2%a?RjygR1GzKZ zL4_@8g)Ny1TPy`Pm-ka)cUob$Q3$qhi`(taR0rOwSL+BBobUqdQwV&9E)gdz=_&du z)8mA>O`=5d|BhsiA*07hMhzMMUIrQZ0m)o#*{w-8!tc=GQmq7s?ry(SJA{X*_V6*! zr1r4PkV<=SN!MhDp2Lr6vM*fj&Y?)pq0h`A|0Lt+GdA*mMzUWE!(sSWBnQH*dR_!? zr%89=uF@XfribUk2-v-do-@|N+WK?Gy80LDAJ?QCVUv4JQ2+Jt3O7P`(ytpEQN72! zZfxY}2;b1c4Cw=!Jms3yrQwD&o$EQ<@j{yI$fAX{x!H~^nj6wwO{z#O!kIuYff>Qb zo#?;8excis!Xo-kBchCL!k>c}2-g)Cg)2&KMwbS|i&aSj`n+JmH-<}CRl2`CQqpev zE21SkO#il6$!^oH$yc!n*qwtJIZKLXI5(915Iov-%2dh!H2v~$$=jx15iR+H=~w2L z#GtC>7Z<6>LQLRB4B%-FJ@-k1$R`Fi-o@E?EwNoJR%z+;<$14QPa8XiZ_vo`N@X)NtDcR8z}Dn~N0Y1_*tUJ3KiQwUDPBFeEl#qxFF6?R z9vF<*Z|g{QbtSvvHzq0<$6E&m`fiH14{q!1YwzD0|HRVnit@$f<>i}I?M-F34Jup;Oy?uLKd#b%`-9Tr1Um2{HHMMu%JyfXJKqJCkKCsjjBvVDI*xEp>yvJClQDLxY`dL#b_xE8%I^mfp(FL??W;XIm0E!DiSzOEcnl^#{0HdI52 zCdjNLndUB5bOIY6YE5PBme$?dlXc1NbbyFV zhqt&A;W5r-KuXpn*Yx+gU9Z!U8XWFSd1URjE?2a%+Ul-rA4;_jw)YQpCkM^&s$_q1 zusxM*X{~N<)jH{s4NZEWy7TV-fqVLrU0aj21O45-TlMIMd-|)px(1U&LzUKO-Ee!K z3}<@it8MS=Gec`yEtQsJe-}$iTWwBuCQ%+9P3FfsdQ)OkWZJu$lUsX-QprI*&@#}S zx~F|G*_<3ori_pE)wOGz28Mc5y#xKWx5k>`p=w+NDQi$CWm|8mslHYl1Wuuf8FUW! zAy-ChRnpU_Zf-J;u@uQvXHRY4K8&2)6-QC$|C$hFD*?D*UPSm-o z9~>MQY)Q4JhKF<mX&u&&TS=PKQ)tJ zUaY(h?*;2c1?Ut1g98UIk?pCWa$tI8$7MpaX zMOW9=W-2t-GGVlBVp*TOhv`bHmBam=teW;dm(B>jRe7~p*E^Whf_l1MMPg2Rz%D>N z(BhSzCaogVbp6Kq^{uK8>z&la(2bR>Q2bk|hSD{$a$WT*g)2gauyHbjfL$H!LrE>a zePBo>``bJEk|Ol)awDj&!X2eO+1}Bs0ypyJQkf`UuAEM6qsd)2Y+I}%v7E-J$_*AM zyc!D52wtWx56lW&5ttpgDl$K?Fi;4k>gGljz>6|f#M^TbKIhQFcxMy1w;+ES=vnxf z#nk!e7F~;Yn znt~Y_V|<44=cP%HW$GHaSPT!oY62CA-y%OKm_}edbKu|Ud1+05XWuaP+ssFz|H!AY z|1jIV{hbOsm^|twdYC48jBL}7k!^f<+_H0N8+HeNYS&e-U)9#p+uxQ*v_YGRz_TK5 zS1D)*Eo1WBi0?0+eLd8}m%!;E+(@8^Ar;2Y7%+fuO-BL&CnxsF$djShKHKd$k4PGLFxHaI1)cO}qCIMZpe%*m~Ujf9ii?aYCx z1?VnGIJF69UV~ErIm9ui(i?7Y<|QzUm}9TO4Md>hJm<`ItwSe2feGw$N+b66rJ;aJ3xq!g<08MDogf>HTUj z;Dln0$V4~Xlsj`FPn;+8HLy*3j^LkSdt%BGCI&Kv16czDLkSK|*heRT; z!KeMI_W51-ng*Yt=bUMkPQlOq4PzfbVLCQ}8B3fTOgo0FF9+IJ;TpY%a;7b*nbxC`B)w9q?b>X!0%t8 z!8a~Z{$DNmi<#j4Q3kxXOz+->SpU3_JJS(-ZUPlhHbu86QlU4-nR;)Z*5E`jFasLJ z*!>fsx9;KXB=n^yCXaj2ukXSB9|;`>8S6zMo>#Kp)c&`+{_`SBrtoORah~%SoWrWW zOn(cj1+l%(^tHIRBoOaXM3I2(WuUN`=c60hhkgOCldZg=6hs=Z9nZcW^GP@h6HX)% zdT(bpN;dQbSiDRW{XSzxBB?E`uNp8ezlKZ=i}G;_^W*URX%=$kKf?qH~RREK7Nyr&u?Ps z7E&!feoLB(UPx{9@i+STcl!AJ2_)S@s?Eo5OEb|6sVzSK79YRE$LBZBbPK7ZkDp94 z(F>^_AAPrv-sYos_~;?^4UBM$;ro-~U`Xx67bMg8{rK1Tkk5B0#lal)3lh@E{}etP z;(L_hV4k`g`x$9o3B`E7^H&-4boCDGr};BfDSwagYJ(s^Z}F>Ng_Kov%1prgp&@{qdbhaj;VTSm^nh zUaI)}XF8r`s!{BhYyQn@K?Z%R{*^o}U#)g!@axpG8S`DG_yaTL-FO<*=QHNhsA@Cl zCiUeEdo5}`bg9pG9L2$n*uh-djqgsC0F(R<&2LkyWIlXfQ5@W&T7}=F=?;9Kb>&@t zQvYTY!)3~ylE}OgnJ*$+DPp<_7+a@FRf?F|N+W_%!I)saASaDh%EBTR3v#j0N@ohn z%e_*$U6jt1aR!N28rPso=L;?nlld7}^C%(`P*70;1a3yjq$f*QZE8GFyafTYKcYm{^99Mevt`|19`{U=-_5f0qgBvs<9cgkB-IMsTBGr{Jdq z_Xs{L_=q5nh|xZeeg#oC&kOyM;44Jb5BD9)y(Rd*U>G_aFBXgoCInXqt|ms5Y8HC4 z;3tWw$CS{Y6a0eUmx!p-uLwOM_+7yt5wW=cL+D=$P73~!h`P?fb*AGKoF|wdqTZJY zT`SluxP^$K=@mL9xL0tDi0k7qp}!*djNtbKPZCjduL=Dd!83vZ>oS; z!Z_X&3`bmgIuZNI9HAEqE)}dHV!v4@^c{lTf`Q+s^w$NC3;vLZ z{puB=-w^y~!4HVoTpWB=VBAH5R|{TG#Qt`p(Dj0?f}Mhcf_ntV1fL*cU;NKP|GnTp z3ce!vE5S)3_Rl{Eor`Ocam^CER`5o_dckHQ_S-h0w+ikQykGE(#44p87y7>lep~Pd zg0BkxhFGK2{}%cWg1I<{qT>?0PH?GUwP3U0X2D*;VZl9u2LulZ{jw@hN3i2V(hipE7mD5G>W@>a*Uj#>p*bnvzjuJ7MhXu!o3zd3QaGZ!qJ}!8ei0k+%!J|Y>{%e90L|muO2tG?J zSL!>0Cy2NnUle?axJ0QR37#b4dV59iRpK(GelB>5i0kFof^QL5DD_*xNh0d}jNn;f zl~NxH@?nnk$}{Z5SsY&_>l>7H0}YqDE}DejN<>|B3Ee}CDz!`Kdx@xvhlL&^<|}nr zXq_+A#WO-bODs}K&maEu{81Nro}f>WKLh_DOXT%@P!~FG@bz;Bf}h2CfSyZ4U0g48 zIdLxPP3Srz>VnU!l;1>*E7c=(9}#uIGwkG#5EtN|T?qXs5q0sD&_{`jlzLX^?+{TJ zKN9*R@p{Zd=wB027iWY%ODxAckaPOWC!#Lq3LPgd!SkKaONgk8I-&LR2^NWGpQ+zQ zL|ya=y`8uM^ALI;5p}_n$dn%^R^cBP2>mr;jZ)ubTYo`vK( z|B;CGy#X@3-ZvAmo(G6n$Kyn--|vZ7w`+O7!+PoaE7s`%X{?XFZ(?2kD`~99hs61? z3!lvYW+L)_fQWqS`xf&2JJQJSl{rAo88Db6^`!pJg>@ow>?pPL676HiOfF*n?BVsSj~wYNUszkk`k4GS2fX$R2a% z0itYSL&`fllugEeGE1ktJ(U{l?HEoahuo~W%cGC>V8o?{QiEAj+MKkGcJYV~B5_aY z@Z^tev$wx{KqdMIQpv=s^|#-EgDyCBlr>iGoQg1kz`-%ptvOlIg=^TEbnbzTW<%o%HU(_H9YUb*XNusc_G8dWY_^Sw8P{ zUN%AB*}<%0jn)2xjM+rpqm16s!)#*y6MNa@c$zO8PYwWPW7oL{G1Es9+yk!(Tnwr9 z4wV?%y-j15y~{opnazcFjxw7-`e0`@j(T2L3dcXQ3E2lGv&rDn{|OYCARX5 zZ7<+nh1;6fUd8Kg{wo91a7)yUr_I>MEl4-qW-=Pg==L@I^~K^RMIW~vRfP{* z9IyT3z+rqC59M&XQU~yXz3uk_+3v-M<0fWfZ$HLtdsVPUIojiNjJ;o=Z^yR}v^m?3 zt{2~H=-c*ITlR2U_3XWXz8xQ*UFerGY$m?r=-c+1EPEU`@ukqW<68!MxYc{j*!!d_ z=jEkG{F+~{j9fS5Y`>cOTe`2D3T z=gk)i1Y`K`+0x60?YPyFKXRX5{zh0pJZ<#&$dm+$`U`SRV|RP+4@SI(R7VexBz z%`|@b&-d*4j#_^4NbSw{a_HNBkAkk!GjRVHd(&Jw&+l8}H!iY9E*Imr-!aSYJjhax z>+_;(&#UK2&{NI#+pe7FcPs#N4!Jz(i+FRQ1TfX%@YWc-i zATQ4$Up+qxd*+&?N#pll(Lr9k`SRZ{)33>mk$Vpvd%hEv-y1ByZ@Bin^_>81_CDM1 ze|P0Pzb8P`FU;x&Qn#O=WBYy9@{6x_-hBCw&h7Pm33~V{=QU%G-|g-BhLI=w#n(gK zj9eFlY`-Tgzl$MBIqH4iwdc(j|5F0*-(=CCv3K0(w_N<1U*nD3F`wU;EWh~5>iPYW zdwqC*m%*M{Gu!V$-*wa_e(|+eH{ahZ`CSf4Gv8IddhUZgu7hdD-Yvd*eq8*T z(*s6sxv!pIwfu7ZjNhw#exJ(XcZSdJE8-Vl=XEoFi+p}hS$=P`{0=}LOXB7E=b)#` zbJCUb>N$!BLDomL_L{DPcF5Uv^_Jzg#_~Jpn{N^9O_gUp*C0O6ZexG0drolWn z`261Q^ULH>j?cSm@iBF^2OZn*qgm#Ak1OZp`Gol8Z>nsx$2NqHJ>RJ1cRl!&V;r}* z_Pjj5l*R92SI+Z$M*KFx1{>|Mm7!z%EwcQ69DK^rFP}&4`F;p{5cQg|_eEb_@i!gn zo6|2wj=yo*e)0dl@$%dXdE<9A`nKOCut&aW#vZRz$a(V}6~7xr(8%F+U54Md<@XNo zjNfZqdtRRT8`D(ty~36A{GJfM=CqFS%V$-4zKblse`fhzgh|-*eF^qDz&Fj_JuWi~&Tw^?e3|Q_c4s zSI+axcfHh4;=^YA{tkUR&#NuJ-6BUl`sBy7pJTAV8ZceH+c$m6z769a(SbC>n?%R< z+XTON;o9VW)r*hG^I@O8w@UE)oG}79(|z1$Zvqbwyywv#Pk0%7{GSj|2kvw`i-$zs zyG$dGAJ&*Hr|>1F-Utbgd<7pGg;&onJ61D1p5Z`gZ8t2+H5meExQ0-6(gaVVK52#RJ@@kWimY9ThFt1LVU|voVOcgYg zs_3Gw6x5p*=`G4~p%=71?v0hAhxlq+gu*>}w~S@_jN#tALSu?YFqT=NrXua5%(H5gMXHH0@MpT3jOg+J#(dW(syN;I# z5woW)_;tj+pc47^v^`^0QoZ+L*@0N{5Q{KIT1<2qqS#XRx)hgegM(z_H6rELEFb}DHZJPUb{}rl-7B+oebTy?e46$ znHyOwA3-eB*50&L9Wlopxv9oX94Qp(9LQzs$VqJF&^b2Oo!fsdo$gjo=j7wO>$qKd z?{QnSBEvA|v6`d#-pZIPt&5E2&tNSl4(-X$$KSmP?47gte5}*D z%f08c{+}HW%`X3Q;nC~6?SA{%TyN;E(B85F{`DlT_a*j9iS9P?{!>bPwA0${?tN#! zby36A6yjR1|;rz>|O{k?6Fh-969rTYC@u<>-+}PdFq0nE#j^WU(U}xldvq z7s=f5<}os7wjhJMGxzFj`sMTVb<3O6Uph};x4b$1!g>0-<<04r&ePW|^YzWOk*LYG zHgxW{oRP^5?$4nB6NmmT6j@Z2={DMgb1&dkar5eDW*T+;er#sh6KB#DX}Y z_ZwZWvCI{=C*?BCg+ZC7g;ZU%CPQj*hIv@>q)rJoQ+0_75>b`=K}H#*_!Lh05Jy>r zxKD~gQBOcQ;DP*W{{(OmKK87OqZA`thd-e%{3#V~BOts9fAX%ypV#rRE{psI5V7+4 z+!)ET7X#jl7W>Jden=Eh%W@Xk(K8uB^j!S4bZdznt(L79nXL=#=q0kXPPXP9g5EW( zCL+y%yinm!(Ngp({_F$ow1tW*ob{oSZV;nvxGW?}`ZRHQC{)s~i9{$;GN_4~P+`f0 zCTc^aB_Gg4U1(9shcr~D4sp0q znAJu0?!u*%s*4Gdz{7r&QeK{K7`0fn=3S z#~?#ZB&#*)w3A#Vb%hLkl{9&pjpj`ZJnu$IY_gO&@g9;_di{_Jr$~i$ROq3CGf9aa zYdxbhOx96iJ0&8!DY0GJ02%t{G>Hg35AUDn;hofuhYheBiDl*OHU#nyOn)w+QzMhjTG|Sx^W35?xe(`0#{ZWy~R^1GyUVz zB=V?ml3bsROl6RvkEKbk59?$f&ZYH=5Uhu$DNzx68ts0UDnjWlc?y?PVWU*oM}>`< z3LEDsTup_oQsE&gY|T{II!|GU3iqWw+?T0v-#mq#RG3YBn9Wp}H59x-zlRFXQNf$I z=L`vNd4G`-FQp}3G9)}3-=>7^(#GTLmMu3RL3QEf2}rUoB4o z?;L=>-2RD!{DZQ?1Hs*uMGgxvNONtnD04#78o7V4a9d#E$g*gDi$@C12}=;UgjhKK zEPoHRzK&PZ+OO8v?X+1pGBi3eoE#p%I98Jyijf=`Or~O6M^dqdq2A<{Ey*ph3*)O+ z$2vwv1}~2Fq=xzidxp2gZdkjux@vV*Rn?86?&8X;#*(SA%59U|N5(2^Mn~&=#(OGT zM*4aND`B;=wWsghW0hAV2L>zKJ2tIewV`@)va5bWYvro=ns{|(ee&jkzGP+l_?FgW zYGAa#t3EYwb23#qmg?&q8y{M|3Z5prQhj~#KKSaCzB;9^&iawQi6KNk*4f^%x@rR= z>TH3uyU)MD*y1HuG+G?)r zYHzx}p{wJ%)`qSwQBz-M=ry#pUD+nuud1tSXm1y74ebpbf}i@P_L|z32GOutf^Qy% zrS;XTV7{(R)NR;^KTU0nXjNN#hpbe4mB!kJ%^pKxHLJt*)-CWBX{bKDjj= z{#gG=%JWctAv{o~KG`%p;8h#j8|p@ew+?KRjB9!Z#y5uWPSsxx(PVpV!ttGLh<2hB8H3K~@_oq*obqQ-?uZ)n1#ajmgVwXvr9nmUPf< z9RW$zph8Eab%P_w+zqMZdt@(}PclPgyY3>VHG6Y)_GTsBmK=iz?fOx<9zC&dZX^W4;-X4$WBj-^;rM{9C;%fRrq z+H@KTl`?fB6T{=llo<1p#>*w0J{wwUHj43~QN>Lqw~5|?abI+P;y{){o0IQlFiEjt zVz`fK)idbP3<>#TWCy5C6N9o7^D@V4ki16Bx~w#HNbnNFw8J!#EM$a4Z@vu?Z@z_R zwTtsUksR*ZE@;~zWr7CiRR-;)pwZxsGjmC==F!2yp^3pk0UYxd0)}O*Pln~EnMe8Q zrAd`2lEjq%V>a=c1WtpVWKZvaurB1muqs~l4&nA;uSrf`Ftl2P3-UHaM7~|jFW&Yd zd$Cwzm0PD;r&(_gFSpLN@D*Ovv~3a=PH9nU@lZU062cc?>z3leBG85S=+cIYJ~-LN z?_jmX5&sZm+o0F>aqA;?Z81(QQ=W%(ZE$J{ zTF#scj@A5lGv`|CU6GF`MR6~`l~~qaii-$*zG6e>L&g8+^UOcWcGGa*;KY{XKg!&^ zN3Vh5KCEW%L9SCi$aV7Zt?TBsomk`i)V0)X-q_hYFx(lBcS4-u;AstK$auV;qZ)j2 z!xO&W1PMIk`=orf>&Nt9ifrLR5>NeyEz6A->~xD>bEC6Ac8fmb7CH+f>s_nb#;=@K zT5y+5!Ef$#A?$?X&aZBTR7u#m$KK)Q-5z#czBNvAza*<&D_Uh^OEL_62?iDvY;#L0 z-Qp`;XH(eu4pbI|orm$uOi8%eT^L65Hn%VwcUL#N7wvOvnqA?1>(+g)<2-7|QG=(j z^SB)kH#-M!ZHA=t4d^;ogq=E+h8)ne}gK>?}IG3DO-f!$M_&ZcfoybK{y_+a+hGN5oS?%ryGSyD;%v1 zbm|vSi5CpG%ftJ!v0v8~?^hO!cDiqarPC1tgXxFutahgz+Px{4-LHli>9%yFu#1pS zX7M{vISrj#1~I2OkXk=~>-JuM>neA>L+0-BMv3>wvN5wXEcFVDPn4k-| z8B`+S~O83HQca3gv zo|?px4?C~q#jDdXd=e%Q^AVU(K~s;`^5X7NRJro<_qj22<$P2VaMSF*y%|bXC)0?# zXF%WrXj~q5*EhS%-l9g_UB zKfuSsoKYN66yWpQM!Gn7O3d_cJ~h(*!T?|X?&%wF@DpIBKA%w2#Sy0l_;@X76h|x# z@Ru4~`d=2{FAMOO2l&ea{Idf5vjY5z0KX!@KQF*PFTjrn`1+?!Ps|b30e*Ere@%ez z-DcB54&HudjxXPari&vk4)8BdGf{KIr2+n>0e&LDPl#t!3NjNckrZE1G#^4Ou{EGy zAJDH4@HYnd8w3320KYlF-xT1>w>7?uBU%IeR-ea;BiaM}_5lCt0RQR$|GEJGx&Xg3 zz~{I1ba6yifX{c=>Eejq0KYfQM9snYo5h(o{+Zd~h?`7t=nn?y(Ey#2Ki>2EUK>7T zwj=n4j5K>vW{15O+^Ex1nVl~_03?5hq>IG6ksqY_+d-LKD(=I6N18i9nY~cF3?j`x zMbu>QPZeS1?|do0RQyiaWB!%d%fxvZ{N>^-#rNdT!Yh2wK386uT_NsM{`eb0nSGv^ zQTqH&TxQ3`Scbi7!IzATuSN3Lh#e|Eem^d=FA|#--=i-U-5LB#@uQEY&)*5k?1Xp{ z3x)R9N&R~9n+$rRI7R7u{AR%y-D!E`dj{Pq7AxBG-!AS_v^Tz23%;(WzQ?~#G^z3M z`r9e)2QO{EOT1Ijo_sGTAy%S~5@CB0Dg~Rp@gT}}b?mH+D7rvlp~7N?oHUe`bWWr( zqB<5<(kbcF6sqlh<=Yh9TU5pzx&$S&I0zSuR= z?1GK$?i@w0Cf0lFjC}4S#BPOL$)v}K4MOZv^xXS6_4_^D_p7Y9SR#2@~t(tbJ3;fn-p$W_+cW}y}SScyZ5N}FDU#v5&OZDivFI$7Zkoq z#6EFU(Qha$L=H2~Q;FC=&Qx?<;iU?jiP%><6y2q8kcfTeW<}qo@Z&`6J2Q&@til6C z>_d+#`YB>Ui0>)-1%_$Oj5#xoDd@l^OWh36_mq3Iz(+ zJ*H1$ga`slO(K?zT<<&rxbC_2b6s=GC&q|aw<{D@5TT4MT_U$^u1{{&L~hYshuoTp z2_n{Cy~0K!*PFstBGy}n!fS~LqElfv5$kD-!hRxx8&o(-#CjQ5I7y6Qy(*j{VqNT1 zcn1-kxl`dZ@oXVJp>T$XPJUY9ej@VzeuWPZkYCL&)SS2#;tgZ)6^ zGeqR$_Y@u?t`p*i3J(*JcRy7)M_ez&%L-p5BF}!S@CY#>#4&}(iO8$JDl8{9srf`6 zplgyopBPf}1b%`v=Kos7?<7XlIDLt+*Bq3BnM$b;jG zmgnXg^aFE1|D{CaK}^vri0iP96fN&KA`coB-9khj$a56>-K3ERgNi>&OrSrC-bt)Q zp3*<+&k;j-{$V@j`4dFU?}a>vFs}nd%;z0M%;S?p%-cPq#1RwBmf(?pEVV?>P0Ply<% zBHlML#A`Pqo=OhJ@ir))oE+FPDVcG;>{b_2ayTlfc8XHgL>_X=C59yYDm)*<4%Q6V_FW+QZ$-(zR8yMa?BI3g% zs zTtXRle{u<>um9wdNMD)CC1Kt`I+={VwUkRHeI+NCMD80`Qp3xQ!GYnVnbccTJwt35 z*@Am_aSWYtd(CeRUWdyS0dhOznoTabz}2K&V(Hsa{w=1Hhz9RKXu;&QRm_s()js9S5f*y<);<_q;c5y$>E-qQ=*K16)8g?EB+ zZ24tBpSRGa3ywlrc;$z69EY;tn8_$O(q!SYQc$i<@d#QD#~kHGcPQQ+KpaPYELsl7 zqrmYb68Nz6(e|G8HT>eZ z_5HpRoiO`*47@>nbkX)ULCCZ>343^Cko{o0?#DTvJwLu~(2S2VEZW|g0eg2C@kNy! z^(OIwsNcVS5IaEYqU{Z%0W9C|Z$VJMNC|4Wn?RfWm^S?4QONH{5=mwHJq7}gD1OoQ zZt&!MzZDpF`sLWLXt`@3XZoEn{PLeEP>y>1PHg(Ef;~Kf`9<5??aBFm`Rqvjg-TM( z?Sh=?cfa9x5oEPr{`O<~ZH2vT{pGVS{`39v*^_>CjM^`sl}*177=H2Z^nAaU1p0et zj{a5$`g_0ftKVK}zZV4hd%*CEM_1pkfWFz^2SIb~>!R(w7U=I`se$P~L)LZ8D!(YGWgU;r6u_x#IGzP~7hg5}asG?f58rP$^zfC#FWTN80{xv;2c{OMF8av|J2RQtG~itw)yP~_^p5=j+cJ>s{M8a{2npZZMQMtrqOj(YqToUrG|*A07|FI}{~FMD#nU;dU%{dy&+PG_Z`#kwT9o#hToom-|ifKuL<~_ zQGQzke)$f^^xJLt<@;Z-WxRYhlrg`smu-J>1AZS?e%k|nt$^Qt!*7S-_s)RdS=iIh zbTkRJEIR^z4=cY{E54Td04ipGM-9K%K$dcxAO6N__IEBvf4}0%`FV9*`PH{SwBIj6 z&h$HJ_`TlnTZePX^vhtfotN+M<9KHo*(`A=<$07b*)1i@5Pt4h|!>{2f;J#?dJmyI!}B2?y2ql2zBaI z;luJlB;P^!)rCBM_s@^Xp>V%RK zN^0U5{|k+e9AQL^anCsX9T2fcPnrTAM~O#pi4*lLtQ&{IqfMhFiJNi#8?MN{l0*}( zn{hq2&qz=svqmo;y?gYYeX|p6JA!^WI@UPlTM6T3L(p; zIDE1|h-svboD7v1vC%rW)e*}O3+8GJvlFv;bi_HTsWDI!$NY1Y@jwr@jo9InhNp{I ze7dAu-C$p+%XI;X>-{{L$AcsLg89<&8{eHsj;?ZER9QPQGU#PZ)^izf*X|^FL#{(& zROWgVxn@15#r3ZHCdUGEB|O4BkSa-F?W$36?YrZS@x!hZ9??-x<(qN>a%!Aq{m*@K zZg9K=#>x^#rOnRg$3f9BW~`*%{mHyUzlsGn~e_FFX!8dk-A(Q ztp9l&%(;kRgay3sgN2fCoe0G^V`Zy#)a6bb;|$P|5@5b+r{+!hkyGg0XvaeK%NpRGA}ghJtSHRsDAC%ja1?hJ*)%QWY% zP$axca}I`z!mBmsP^dV(QFHFbyxOce_k>ErbSNXZH&hnx)||tkQ^SLr^Oex7@HLuq zUubstdd;~%G$*`Ia~=rI4d1RgUk$~=hcxHGP`Q{!N0BS>rwo_5GGqe^%*eHXC)iRK z`X{!8B24bTuw?~DM2z4vuJ{QWtZhZ+fugj<+T~A_&7x*p@g{X&hV*$-_hqG9SwQKRH)91ucY)M>mAarRt|m`Y<=g#K zY?q&!b1SL;y4uwXkCA%qG1q43LsGvaPZZ-4)wql+{*UooZOkwa2pRs>2IF@nDx|~* zl-MsNWRUv}M(IkNCnbvTL}xuhiID8nBL;f~(u#0VKVp0sP$;9q(>aBw^A(=n`#Ufe{n_m23 zQ^jw}O(|?rA6!FP51YB}lu7;N)GyEJmwWn6bXYF+#Z1UzjnmGRfd?1w&nz4)IgcNoM@l`nKT(xf-tJyPsrgf8h{y&LH;lZ!B;omp~iWwbLP7gN>^*hwJR zQ=o}8DeG(8y8R2p9eD$Pj-w&eQd%0Si88(HW@xd9-lFU0n^8_O*?wUt`hc!4ccPEz z`pR(hTe`j~68*leuPKWDRM(q}qp#`u#u8zF2765;g+EE`ccCjwOG2NDo{Fk;bh(Ir zLf6~P=y|%{5sF@{>sy>?6YAV3L#c4|GTpwlNJNgn?(fiGFDWgv7e((;a(0!7enZ!* zL(%W+dQCX`V_mN;ioT-ji%W#F02z#8NN{UM&As;!d5>Y?{ep#)m!-l5!F9%>kvk*{ zmlF&3B$gr<1UC~FEnn`Ef-9Ouw`+Z^r~Ps*uy8)JaGJ7cJ=PNgeS-u2ss8LmvHDD3 zjAXhum5Fr^WMZrPwxqhcQeCn0CRMDYqqN;l}Qh7?P$oPx1};wLz&L@p={scT6o&tF*KNtcfwb@ z^wlnXwKoiO4)-DYq4w6c#no#NQTyuc$-cqflo;+GO84|5`p&J%jA&?VtzXr=TCCn6 zVbki?)op@TVpB~{bZF~9CM$;1{n?uHJF$ z(M!ap%g~Z*SSs4`8_pMvwXKOYYjYwOu*GL%nP_ck>}cCDm}*FM=ORUjGS0=dh?4;? z15y&&9Sy0*{|n#~M%W+lmXA4&B@UzZdoYIBWkiGlv^bdT52u)f~UZ%y@g zal}3Trc`GNBj~klXl-rm&!#f{$==q1?(8+mOv-1mwRPigc5pbWO;W8j{dazmwoI~r zs4tyGGNqG5vbS@%H^re%%QejoPA)QHeX43jcrQ7tK^9{wzVKL>HeNo?qFo8XucGQ=RlDHl(iMXr{!P;eItyTw0H5W1C24 z2M31mw=X$#mCQ7Iht;qNJ)UZ|OF7Qd&P*p$t<9}zu3sy*q_acroJ;j5xAdkI@mJZF z>+7(;CsWBSX<_hIkf@DUUnuNOY;mdWi~1G|CsMFJET);o0&m%7nR$vh&6s7JZp=33 zI_1U!1F!Rn0VU^>hcyGY~yV;=$E(V zpxk7BdCLyU@%A0GH<|8a@l6(so2&dBaJ++l`4|vv<0C;ZFFKYlh4CCE#xY7b#dxoH zI)P6%Z1^kP@*Dd*dxx>(<=@r+mJbwvGu!F@P9eOfmH1YsNj(X*%O|0BKL2!VTiT8# z#VgTVzhQ0rmUMr6Jl+m%CIXK;xL;(UjVDXbn0oZVvvPjZR(@>AHDx+Gp@=3CvV<)k zO)VS{*#(g+ov&Co?CQ2{$NEt0-fLUy?4l~PeR!R0yTNeVrq!VB9kdlV))(1kuXC(F zTo<)_E@D&cBvD$BXOtMF1MzA&#ncvDQ?%r?fFiX{naWnV~b=UjWngSO=~+0)~I8hfS_cW$)jfoH|-88V2f zKm;$#2=23IIo)ye!7!n^!C8cH zirbY<7;G?ZlEXD~(xG|FG;Axf9^=;pscLkc!%;2c^wYZi48=buAa@q@G5vxgzu$7r z&ynV9l-U})T&m~LbzdXhPh#c~m??yR&s{HJ{yJQO;YV&*m3)8h77aK<@{EEYJ;Xe&j74a79JoF4nkT1~;`-arhaA;$dV zU#Rs}Xcb4?5yP~YBo~iCA`;nXm#|lb@qpK7q}Lmr-H0sxF*5b4lK;4weHZc;;+qcd zB@VVI^be~TarOivxzVQNMkxvQo&ft!u>X=F9fy2Tq44$4#K>=j=qH++noeE|7lgc9C}K(N5Di8a{;aqImZ-O#pf;=o`>KDh(? zp<~?&vT)L<9&`-*jL0aq0c1aJ7f(9ePe2I$UMJ_~d~SG`+Mj?zNw+->I|n8tCoN`Z z8LBhgY7|wOj+Enr#EkVV5xy%`2Ix1?MtQ!^m6`?OUlq-Fxl%JC4wI=0^*7^U z6W>uv@uJBQB3&WrnPLF;Nps}!3MyLj=+nfP@fb^fo8-?H{0L2&??$EOnc`hVbLEtp zG4X<;`JPm2&KHZ7KK+)O3xuKguD^3|_~+Uymwe2}kW2F&t<S!Dn8%GO3fAGdy3C@u~M^Mv@1T}!%EEtJYT!^Tz_lDT(n1^ z%#}rKAYLFuvqByflg=mvh=uSW5wYHiO5`F%Pgl4=;bMh#3fC*_Qh1fZZ3=fP998%wBF2@6<+RVA2M~D}jt3y| zT}A&$;ZGI*QsHljNbWm|o=`X)HfiS!h36=|K;deItqOUvN%;YVUm#*W-Js|(g@=il zUtd==4;QKTBoTxAoT6V+$P+&Dj}tKu|Dy_^OryZVCnOGMwMW3tiB86*- zn7o%Nx?SN_3i;Cj6YFTVqW3GjSK&VpvA({g=pQKL8I>6m;%ACJs_+jA-zS!1UE#Qj zah{^ELg8YCb;JrGcM_$4!d9P2mFy#})oi;ZGF4rtp6hzN3(z zJQ>Gyg{Lb#OJR+|PbzFw*rD)Bh1(SFR`^AQcPspw!hcryw89q@zO3-q3g1>}Va+i< z7VZleW{GH)`+?j)(a5cw>z-RUky|&{E4OT7jEHrLp_f=mgffOgBDP|=9#hRxp11(>lZgI2PDDR`K}7sp5EJ7T@vhXC;hv7PHK?^Ah(5C2`D%Y;uc;5AEoaILX@7 zliB~fhN;4!EAIypQwjNh&oGsYJJ+V}uKy1qjdk>)wbuTaXEc<7?-tww|2@6VNA++tFb)MgQeSUG<_x$pQy8iwafo3eaXnP&5oR{Zi$}b)rWYKb;MZ3Sh z5BdC_0!hlTzw2Fl-a4uSJ(=HxE9d#`1x@|aaIt8=E79)v`wgF8JkEH2`TJmhf3whQ zla|~++8*EA{ds;?`NboVEL!e*$oc&~?(=&FBz1ppfWF`Fi=dY%TLf+I3$C2k-w+t= zul_=<<*tF8-|rJXzZ`q*m+$3%zeQl^G4uQVb--^-`HfKsMf?5lfZu0)e&;DU#>;&9 z{Z_&N*O@Nb-VXwPmngsUm7tdUUcm43KED-^r5ye8hwpyB%fYBswg}qZ{J{7QfaA~3!$`TU*@Ny<_0y?|eSx0q}`zZLNNkn($u^qPzB_W{4J`uyUt+VkrK{PH)u z<;oU;@v*#*q~M=7uU=Gsb&Oi>B!v9)>J6XYMX*CT_V*N2{CWO4XznYzXnTdOoadK6 zHKsmpud--4{(l&LzrXYO<^D@K>RpD4-|q>~x(_r+IhGBsoaZ-&n;-S{T+nj-U9{it z37=oQ9(sN+bnSWjRVD0AwtlMue%qB_eZr#s@;jK{@B2Q#=llHff86o+w+r?rTSxr9 ziGN;y`CW?rU51NA`{jG1-){($m~wnRxKPQF?g-4Q?XWl5eQ>iY=lOkD`PC;v+V7>1 z^ZPCG`Cabw%jW_7^YYB^X3U2!+FrRU=lT7O^1DI_YPq?A{+9Xtu7oV**x$zk{pEK! zybgOs+j}I?U%oF>zg|gdxvvHKJICjD6=b#FPr3c@`db2f*LhxZy+j9zCs#MMf3Qb-|u$`{8nS^IG@+y(s|w+u=ge&zMfLH2-@CAz+M-U zGKeOyApau;J#aU68fa=$@^bzMgMlMjuW$5?PH z9Q4bzXu>DQ=SQtW_KUE0+}EJT?bX0MeF>Yq?r$sfbbntA*n0{ORku$v9?u8tHDIIv f4(u?0JoD7{r!Dz&uU{`Z~vX02J1y#v;s=YO7mX?WK+ z-*vvZtXZ@7UhC^)CXbE9V#*#dHAsb&Qac{eoK(4nLF#14Ha~K6TaR@;T1S7NMm_aj zEY>o*%P&6t{j>vWUeUVPai9M6lTV9UmB#Ydd$hLwxp`Uv__5=ng(CAO$c%!Y&`wddi^y~l zncYUlv6Iafh)jXVJPnyj9kWyK>77NYvq(J*sVYA^*^EeKMCuMmjnOfMwwjANiBu<% zy4FY`s!&Q5r9~<&QY#=eDw3y)Y)WKOB6G2kaq8EcO^QrXWTru8bdV?0uFVYzkxGcv z8IY>-BQK4MR9vJ^GE&jVOJgDx6RBR5(vgStYtAZ>QX=)~?+^7~&$i}AO)qBuUDJkW z)~oD;2jdFyv=|I~>TGQ;See_w_FN+Kvmq|@` zl*#UP4nELaVQPJ)9)svRIt%$~eb>PXJp;8Lhs}?yZi}r`>toKm!)r#&nRj^2i0SnW zXP}s~mf;KpI&#g>w9NZ4#H;q<5A*rrA5m6)`^zo2wH$RV*GHf>{IrES+mN|FyT4FnD3v8uREfE~-Q1l!Zx0?+w2UjJ z%;H||3NY9x!$>MV_;ggJ!sIbsq)Yx7E0w%jI%{$tUC;cpGs^1(Gs?J3MvHWb&FCiK zhZ#5g{24WKN+hQTD&~bbt@vX+8)ntczRHYTXf&la_E~a=$n|=KWpDS(5z?l9C=LGJi2`|6X}Z_?`~iH zUmorHn&IViIHQv`lO%s=N+=&*QJ)+M>#d_`CMnOl54tT?ea_?NO}z zm2GOB+A!^dPa9gA)drQ#;NR!)Hy(eP##p598CfGkev8Ovu7o`PTJZPWl^yEb7CUZz zpk*b)I6AUzrNc3E)dJkRQLw2IWg_6e&~p>-ZcHYyIN z3TCAf^hhsze{U)2_PXeGMK>OdW$!o`QzM~ot{^SQZOfHu_E(PCYuACwtqTbSiPe5g zw2P6MB_Fdiu6b;y@sW12bL~Ik-?Uri+U)*LD&w_}SsyWi82V?tNUvKqWUj5yveET~ zje%nUtwWih=jc=K8|x3|9)IAhjWLrCVP!*4!%rujKOvb;gL|2;pp$E{zRf z92ty?Xo-<2&{5(#EK%A~5RPTnzFGCqQUPpdkmYnKtz*T5__@mAil-CeH|MOmJva5T z<*cJQhwm$`SJNN4Pk|W%?U>9Wn|iH<3zy{R4rIb)MBgbRj(B#|ALGZxDx=xLz5A8X zd-nGE%25+$0xM=eCfi={j9RnrWv()9lDiKE?TY(<(|R4YYqQ&~`PZ7XWpi!z6!hK# zR-5$U=AP|iSDB1=+6N!$6%tXg{ScmNX0g_R7jT-hmy%M~VdT1+LclEl> zyGOVA3F?iN$6?evxFXv*g`+2j4SnB4dvVlDDRakX?4u z7)xj+jK$8A;oREn%&k0cKgUINS}-3cRg0dFTQDE<{BU$Kjtkn=GQ@kn1pM%v}aUDNRT#_Mpp2%jrdnDclR>y;bURc6-mx=o(? zd+a@yVNYdkbRCo1R`MUR<*qeUR`2Uzg@MnbTKnKrDX#O}7`b0#Vk}UD^s2o;Wd`-c zdQ(fbsz05ppt~Wnn5&)4JgyN*p$_wo*vHjra^#g;u-Xmfa5dF(Sm3SRVr6+ZWesIhrw zU4(a4uDM2dSLf$tuF219>43+5XRFz+UM<*nXy_=n`o65S`6hd3%leoy^^Nvr%{j{2 z;NMCb|6=n7Tk6=n(Jc$-Vcb#jUhX<%sVGySl39$ASeB*S^&o!wd*1Qpt|xQ56Zfl` z;I7uhVaGcyq%bF&>jUnG;3o|~EQz-^V|U+BdQMWjE7#W(i6JF1q;w3RBKr}x4*6n; z^@yF&tye11t?0<3y7h>icO=GZGB%-CmoBGwIU|KTfrw*0J<}C^w0f75`kvEQslt?s zO99PyEsv1hA}T4P(mhZ~QKcwQ(PR%_MX8>C(S%-f-AkfJXvIPFT^PNZ*AI0E;$QX? zRj8^6INA*8f8%EYVzD0a#9O2j`$?+guK}5uFuTVSf7Q&7H8XV)AiV_tjEh6~m1L*s zvHO!5em`X;3m(8kb~K28CGlV~o;k^K9!e%NU$C6-C)1fzEvGG+$((LE4<`#URhF|Q zS(uq%IscyQmYHceTa!hZ^DXC*WY5ez%lSdFIJ3ZVewgf?skfYM$v&AT%lT2VU*-zS z`Ejy;X07FHPac!G$#Qlivzc#N&ZEfznL8}!vE;zaU6%8B^2E&dEN5qOQ0DuV^F(rR z=Es)vljM-hW0vz|vLy3U%XunUnt9Q3o=%o!c3aLf$@0u^E$7+fh|F7-^IURd=6@{b zr^(YZ7|W&=o=={c`Pg!PmOML?L38N#c_CSm=?X%(&x^^?nLd{D^JG=#Xv_JJ}VN>0w4X*n+^r>f4hThM}kis3$fPBI1P6fd|9CG+qXuSm`W zbV{b~19bid{$Y1j*FgsgZeKh_LxkFPJ(%DrRM2ATOf<$K2lVMrCl*Qfj7 zbBRQs81+FWkBgA;lS9&2uh7=l(|T=ay*6sSHfsHnsP%v})(vT_pRKLmLF?N?>)WH& zw@0l%8nqsf#=0Sm^>>hg*oEJv^@4binSyvEGX?QTW(wnx%mk#dZb)POJ#GCFTAxVk zNuBqJ*19TXDksM8K;Bgk{OP$WcHvGc+)xmNb3=iIQ!s@JHx$r6+igySOs^t&qvo>R zzD@EQmW=CWG^B}cfR65GbXM9qh_1A=IE&v){ZiebO?1cTrr1k`?O}A=qtR`TMi-DK zx*awg6WwE$G|>g5dWgOaX@VW7gZ(3Yj}3zz8x3}>6Kqc%>?c%sI}G;iXs~ZbgAGU% z?El#4l3N(gyOuP;2BZnrkZxu>C!jPZ40cX5*f~zHSsm=rROsI&X!rhIBJJM4OQhWc z(gb_7=Ca*&u*X``1RIbhSVOv*9Yo)aVX%$SU>i-adNz4XH^rG$xG@|vH`-pE(Y^Xc z-K#m9Y}ef|7&AX7xlWVD{}63%63smu4w7fBIrTd#JR5(9gGBoupcO8l!d@yUJ^Ag8 zbM`Y5gSEt0DDkeA&=cIddKepttd>|!iFkrGbkOmH9*Ww_iCW^Dl<27?bR0bsVH_s# z`zUb&CCunPAt8;HXu!M;&X=$fF;4jf)!2m(QQ_=R;q0iw+3ggbpu(b1VUbmcUrP^* z64EVV+TkKczgRo`IrVP{^=}CD*HQllt?#B~9~Cx-3Y!CkO;p%y9jXUH(yie;)PFM6 ze=^X2oC;4`eG~ALPQX2Nz<;Cu9_pK`;2y1SJebDsfu&vI-O$6kfrl6A;a#UndWCo4 zDO7kN8MM+1NjuAFg%^@CrK>ln|8q?mhqHA^Rn#w_zPWZ5Sp9;xsZgL5z|H6xx{D># zsX}lKY0TAYb8~5~EHqaZnCnJ`GOM2%5Fyj2k{qtN9O*jPQ#EOpN?&^qXwr@Scl13V71Vt| z%J#~eXnjD+_DXGTpeBv}**f+QsDFB>e|l8^^r-%sj=srV0q+!Ng!(h0`ZEH3eMy<+ z=o|mXP=86Nza*-^B&uKM=nv8Hmr=ht)Ni)>X6|fGg>$D-7)OQHP@y%d(ArMnJSsdK zDm)xjc(|QH4Hcdb6`qeOJntx&99~X^H$sIstU~-ww&5E=4s;v-x03^t!*5Xk<52(O zsQ$-M{ZAczwmeU zZ~Q0I&|e?wuaD}lkLrKZ(Kr5kQ~&-@|NcOK8|#06ps(xyfTM5xpGf_uLj9+r`cFmm zpKhB5kb^ZU-(Kr6bQvX1xe;}%VAgcd?qi_75PyND9LH{f4Wc%MU zoPP^D+5V^Jz;2p!=fFDZA0O%;AL##*`o~B0PjK{2{A;LxMyP*Aps)R(5!FAdo&E;u z&j|Hr1p3@tPss9M|&0^sZtDhdlh4&*`fvx)#yR#v2!HerVv>&!J_X*9t z9GZJMYVPI0+zT{k$iUn$9dozq=n6VP>LZ#n>#mQixdI*CN7h_s9XpF5c{$e6ebR~B zE42PgI{VbIK15sZOY2|A1bz1l8R@&``tya1fBhLog>j+6II9rD+Xs*BNM&8<;mm{2NlK@&<>Q$G&s&GrS(nrIJ@_g(oQF6Va_a`lX|()BnPOhG^m%nb@tgL%rm*-g_Pn;6O5IJT z58|I|>2wV$)L6_3T`R6o#k`Bw=PTpI+~m~fUrQF(+4C#X#oX=GU|pg1pmyz z?RfI;Ufq({75~Kw+^C8ZDAvO3;>A7e`8Sir$J+B-)5SyV`E8lv5%&C!g5vS^d{d!H zpNPy|h5~$Mgfp{mPvrJI4{o*d;HEeaZeR0w$AEfI(0nST6z2jS+*{=_(17ChB@fHz z4j~WAf6S0-h@h1lEOb_o@$#^8+=Jp_k+U6-to}DF*E0&rtX=jP9v?Lz0Phs|d`wC!;y z3l`KY$c`u}8=jrDY+2pu+3Lon^XsbX7iItD)P=)JhnJR?UZ^ThA9~*Mn#Scr7p=T( z+47;I8XBsqo2rLSUN*nFZYZn{onAfvlI24u)zsDvojGgD@UpSPR<4{|HFo;YvXb(W zVMD8GF0GwkGjwLtg6TDlwGE5sRyEdMTGKdmdE@*!%bS)CFN3F*bDL_HmduB*Ioj78 z?Q2feviU2PBKqZXX3iR3Iu;Sl8MCr_X+vF&T2a5ec2PZ|pTD@eQB_TtIcoIeF>1_I z4Kv2f95YMtuX4t)P;~j?WsOa0MQwf4un}{c6s2aIKc=b_Qe^=(OwF89IU^v;V0%nR z4p%cnqFjv`7gDFH%E~ElXU&e#bXh=u5wv4zq^g`cD`1|crq8Sls9~jQ)Qr&bFc@`0 z8de5Nj-z42Nr#Sxm6IMGT4Q80%0qgD8eKKZG58#qNHKVJShXvCrhXu@Om1WNPaOb={IG<1{r^Dt} zE~{TyyGVPOS<^J3a@h37n&s$wHH|1MYsW5g*~8nhhr8_ZcINj z(fAYcYK%cj=wQmS1vSGQFDwsR&Xp>2%7b(}WtGcTFmf7nO2^dCM?s^m)WYidE^F+v z#`!f1(8U~aTjn~mWy5pGl{;k^dx)!US@i;^&}61^+7z91p(>GX(`=QYMpNUmI$el} z!cyCZ(fe~1vR`^0r&Y2ywksSqwt9J!6BrD(D;eIdq}(g1tgESRM1V6eq&awnF7xQ& z9$ju})@@l`bz^PQWsz8hP0d+cmb)~!@bH|%!*dIl=Mb)}TxkaZPN&*)(`eHwSDH3F zuVDcOQdRBp>Wk~#?qtem)O=+{O(fAqeSCFY-OQT$<;ytzOqnY->uaX3s9RpcKI<0i zQS1&RBR;dP`chwZ3R<mhhTh-B>fsqsu&cxJQ=V7FQ~0wG}>HtR%#tPD|0?JldLX|#^B5`hKr@iGMRzf zC1gfTLrqg{6Y^v0#Wlo8x$L?A>_xI^X~X!K~OB+`z209;;ybjnjuetO(0aq@ruCK2# zQ`&@R7`U?O3x@4FU`LvILgm=nI&^CtqcQA-V3GtqEPoJ$3213!nW~+?tf67q^4g}F z2AOA^qU8~6$V@>rX;aMc* z9C}Nun`-BqRx(oJ*;Z<5%~y?|u`BB5v%^%^g?=Z@(mMLeJ#*O#T(dNdO9+=r!TE~D zK8RFwndJxdu5hlWNrD<`6k8gb$aq75r{MbF8s4*jElCCl-V>JQW`EQiB_7S zuSh``mdkQLbA4tFaiC7X<<6zeHF%Uxj;jr4PIEZXdDWk5?XY%c*I-(e6Rf$-M2p3?IWd!6<)kVd+1SaW#;J>Io0gkd z%{i&5=k?{Eb1yck0ylNlHPsi_su=J8D$7brPgAM+xUZ>MdCJn^*aGS_C8IjWyD5Cl zH(ne+LLC|F6YCr67ds|BAa-I5-zUbc#S|68=BO&-jzkguKE;v5mu+LKx)oykOJScX zIQX^3(cSQE(rexr?rxsW`Xe&n?yw`}Okm7i_O zj64`Fk6Tyy^2+Tj_DNTsTU+_$vxXPRxsAtdFK&bRZJtYx+f07m4p%N$dwrg=!}a_B zv)tj0%QX-Dv&*<;>5rLQF&ApN=v;WX zW!y&f=f}g<<)zk-FIUXmg7vS5R&GUqe5|4P(+fNa^}}vm2_O^;{z+S`6YA&Jt-uXv zbQkr1a|8E(&30}5e5Hcj;gZEn(uSq2)r3#0pOA;Snv6^L9#Y(nI*~Y}dE418ov4vJ{W8!^N_6@h}9aDCTTlNQ2 zw!tlX!<21w%l4YGd%{>YCVp+oHnS|L?wzy?KGi5(?eLQ2zcDQ9v zn6f8a-5sXv8Mo|*rtD`@)_EB6*M_oA>BLJcOHE2A9=M_;6-#$Xyc)~A5yz@C7AF1m zSS(dou;$!U&vZ$upag1@Q%9sXrur^SowzYIcwuT}N$SkisRH)haLpKF8bUU;x)fHAzxuIUgZjI}TrTT$=(nN^PNOgl^ z*Yw&{FJKp*PS&TWb+`1CR53~mOVU$NsYen2#8j8`U8!z6029H#OJk?>CR<6#PP@Ex zO>|zED%!!Ypkz*9?ykUWci5nL<}6G~48L9L2#Ism~SKiv#P22OL-@(=lHdDS6n z+0WMU(Ntek%f9JHrItHvEzuNR)AgyNOnn}e6U6`M_LLatm);@uK^22W{s-%`J&~u? z4qcz_CJeUP;nrtI>ZnKAP>6pA>SGN2Q|ohG@*l3x;kHjt?dCa3`#-`G$+l}F(|;~QG^P7Ht8dwcyb4}i-vb(F!AZ-3-xrkCNJAGBR=#;$O^`F^Koi&CAY z$_$fu`|^pYKIz1*SO+Aq!1=@FB_wYH*$E2|Ob?w(690u^-Z!1NQ)Ko*2IM`ISu8S` zd#2c_Vxpc4j*dp;$_B9Wpd^3dD(D5FBRI{WaCQqMjAC6GZ$(LFR;J1`1lfMatz^#H>!6sE!k} zp}L9As&i44L;Yq^Kf#O2s#$Z#NmN`v+RElI_Z^t)RB#Q9rO-LJz~vO3D$}Qs-{j@= zF)e?!$QNn(?Ud&!Rx3Q@|p+Sd==Z%u>)=>uKH4DVFM9&;mg{$K;56 zvzFMIIvNs3A#r+j4Y^64r6(cRso=Bv-vg~g!BpF^{7Ls+u=^FdZ+@S9-A?Y!zrBcH>E@qG3)!Kinc5DvW=J zHC*SWRa2LS^PDeHSEv)oF%_4#1&)~O^!R`f*+m6s3H%$5a#6u?CQ|0asR=e&<6(Bs` zgydJ-uhlZgO`4R#?F>7rzF`XQlH5Gus5-LxM3s55cqKpMOoGNz^a86&aL=T4#mUr_{SWI zhvl)k3;VO3H4Z(?w0=hUhd-nI^Pf@v4ann~ochdd^l=Ww!^+tIDf|aLKA1!Cusl9( z6{mg1ez-S>;$e9_m_zZf`r-Pnk{l=0!}554J4Iac%#CozW9=!c=nT@s^0+65;$e9_ zkVEmXJl@dFB&X}taGI7mtK+Hp9;@hHt;}TCvEp{C=y=4m$gQLznTT>veJ@!>$Kzos z{?RIaR*zS9m*lwDu)_)UHmmqqJwBopUrY5p7gufU>Xl&05^P8ujjQ({r0E2GIW|f1 z?`2;W1O0gM&Sikh+7ml4@R2bvG*x^qZf8rlVqL6FWg@Y3!a{?K%0UykO6v-$Gq6wk zs#Jem5RV1+0o~uM-i{om@0qcm(V6!mMrJVZRLC5Qq7q8tqUEpbzE||wt_071M)|#; zQT}g`=bl1W)UinJw6RZt$o+QM&?A)W(V=9UNb1%dw$=4v+z2NE& zmN9Q0QsR9`6p4-81M*7TrFJawjYCS@(N4l&lehE=Gud&@TOnD1b-2FI=u+aX?Z49@ zcT0!d$0J;SXY7Rt*Z2FY4!IwK%e6vgn!bJLg+9Q|rNk$fEW|=Iv9=f^2siN`Uc%1? z5-lJL7Nc3a_%ZxjaV*sr_dpzVxV^zp%drN07D8|~31gJ|_S0~uKQVPA_UL%CJUMj~ zsJ@!Y;KqTY8|&0g6B7?z!bNf76^Z40CYIfKV|ic4a!syS_+gfJtmBt_kkAy1l_yr*oX9?BS<2%7Wa2CVe^LFc$3NcVAMf!`^!WA%Vn!^XPWJdGd-_8>zF)tg9)GB(U*_@c z567(k5gwnPo`*+5o#ydR3z;}e;D=?={O}tb;gL}1c>HrhCe9N0Ay-s?w8tOg@yB@l z@g9G?$Dic!Cwcs-9-rSx3Xg<3*W;fXGI5qrvpoJRkN+i)|0R!qfycK$3^QU0b&31xH+cL8kH6gGFZcMDdi+a0{$(EjGLOH? zjAf7#=|>hWLo_`mY_zw-EdJpLY!zt`jM_4vQ@_`mb`Z+iSU zJ^ouB|1FRICy)OpkN=Lxf5+qh+2jA&;~((&2R!~?J-&Xnav+mXfA{!*4|qIDsE<89 zpUNB_SZ&6l*KfTv3k0w}_4o;_(!wL5(jGtU@jH9`&K|$e;}?4T?jFCp$M5O!?SlYJ zj0tsw$3Mc;@8j|Nc>JS0+CF%|+UKe@JQ8Z4N1qrgK?w`_-Tt2OgnGR&l;>*uphvR@ zP@doS?-}o;UKf3S*S}}HKs_OJg{HeIK2sY1>qjT_#OsHy6q-G;XS|nrnlaAb({yjO zn~je10h&HqwF%Ad)c1@ZuUaDflhwQkf2fM#7K8en>3YV?)YGzlAEN0I`jH2r{nHe` z%T0Q)=AWtlL+Grg&rxfH=E}Nfe6%_qwYDm)Xxf1Rfzes&q__H-#txEVf3!K+$ zx<=h2@l4fpt=cC3xl->LuTwur8~LoJ8`M6rXY4Om1$=4=c+6AJ_@(Lsv2Xa7sW-$P zzaQN*zDm^#ZTMeTVNK%u@^_W`eI%bPs&hBv&+xBT>!iMhzDfO7^o{-XYOB!3 z|1IkJ2>)B^;t2mXwNC15^zTqhgf{w{R8@q3k2)s8zfTnvn)rC8{uzJ&!t@bN7S(qdYjrPw6V8c9gzAP`Z3iM;Xk2%8sR^sCPw(rs#hi6(Yk$} zSLaB+4gI2eO6c1)f0x=S?Qin^vf>l@SU*F*s$Ph@^sm(S#J=gDd-%m>EpO<(>bwa5 zcj{jw^qcB0V$Y0^x6~C9kD>phPR7ra=-<%qsMn=`82Zm@Lxet{&J~*9weA`Jt6CI^ z=kI)Pg0_b+!2ei1D)NR_u@wjWPlBEGGHy9D{bf0lnB_=#ZuxUn}-aJ1k= z!Nr0Nf(TO$#<@ncrACZNjTqY+F~?{`qpZY90WMstiO(y=eqDgavEN7hnNmB6m|Ve9 z1xU`XiP$!JgZLu;!7-SPO=Kq{vT=xg1p5j07i6R17@XCh1`jZg)?pkMqlj@d5fR4~ zM8t8E(5*t>PlWtdB7?&*c%UFV1CGIi1P2Qa5iAib73AcOV{o}3J0p(4BLzqjh6l?%iY0MVB#1Ip)9b#mXBvC$|nj=7Mv> z@BzVx1lt6+2yPYpf#5d5ALD^yIF0Wxj~n5S$`- zf#4!RzG;Q}T)z_eN)_U_1vd*mBKQ-*{}9|G_y zk>DkQs|BwWyhZTaf)5b!_XDAy5PXrCRO&UMUl)8=@MA%~{~(S|(2Iz;juAXXkZ%xR zIUoH`Qf1xo#g(7zV^gWy5IPKcd;dJ7&;EL4im zh-djo!Eu7;3)ToW30_I;rquO9-zxYW!7apMrFIDYtl+DHZwhj~M!yNHn}|IHxz3AY zu$(M(xnQN>bYdUmO=v#4n)+Pt5!VRbEO?h-o8aSuFAy;pUlsaw!To|C6Z_+xHE2s6 zpWtzVrGn=OP8GaRkWcuf-etsN5SP$53Em-iKQW8znb405{#=kxx}}}B1wRzzGh$iJ zr@0bOBo4rQBJ>%869vCS9Ee}S3tcDpHNooyHwfNGJP|LB5}J=UrJv^oUn34u>UE*{ ztWom+MjVWGMPDY3pD1fQia1266ND}mJd0R@_eu#pLvSt;lVh#WO@eC#*AdHbKQ8ol z1bLrBzfTa$mHL^`uL`~?ct9|Q`@T3P-!4Sx^%mskTcpc~BeC8SdYs_-f;EDT#M6~p zCG<6dw+enoa0~HFj1Qro6?}zwwo?Bo^dAHd3Z^i|;}v*TClPV=6Xc7DNRJd8LmaKt zG@&mLtQA}-c#YsK#44pW3jJL{-v83>vx2V*zA5+~aja4w3EioSk?$>df?&B|rQmep zc#L16YXqAF*9hJ$cqeh9Qr{JNtKgG@FA44?PFCsh zybq@BrQi&~YQcJ93+~5-UL$z3;9Y`kf{zlf!@Ml?OMzdFf2$l7->ecGPlS`ng42nJ zb(Y|4BAm|=oJTxHsRe?IiCKkj#29QK4lw(M#FeB6Vjd7|CZ4F&TEP|~DshA0I^tlZ zZV_xHqH?zjZX%Y*z6x+NX;k_F!8T%<*^eY{BaLM25Zp-|q101?&k;u|^@89o;^|7g zBDkA)rc!$Z_Yu!F`>w>dNLS!~P;ftSv{DBI4-%`eE*In`KG*5`dwjqQ>G5cPK|auo z>udeuRvG_e6BnZW1zU)V(f)$#h)dA^ zf~~|lw7=jcVm;bla5J$1?Jw9yY&84&#BHRT(EfruiI<}N1)n3XMEeWwB3_R67u-!; zh4vTRN4x^#U&1iqYb;SG8{(`N<2hje4 zn}`pg{RKA@+tB`kZNx2Tf5C0Ut!RJ2ox~rY{RN*RZbSPE?jrse?JwAesV|jjLZ|DOG#&ynGZl$kscu99`tO|0}($F zv>wkV%D4sH!ty~%wF>`s;$Rtv;J1+;qLdzQp!Ikwk#PljH~FQQKSf`UpE4OI;49`I z$u1&-E+&qUeh+#OX*9w};h#x7UHUQj(@CF+b`ZYquV+g?1izW(6-uoWzV2_Mr5}Oc z#_}qqbpHUY`^Q-1U*z`@$K!h@LVrY@h;f_%LcWNIPLUOQAaN@CkI*BD)6su~o=lv9 z{v-4};wwkA!}XxDx$H=sm>CF%Jv9pSVgX#eHMMpCn#^dI;Tz*o=N8^bq1| z%#%V_5Z9s~2|bH=HRe5`7ZY2sz7cvA@jA?7La!sX=zYXnFusL8K)e<8NCQ!y46zmCTj>78+c3U`*8AbND^(#hzaPSRdzR3%iJO#K zEVSMqzZ>I2=w{-*7#~94Lc9<2uF#u_n{j;=dI#}-j1!@E5g))jCG;D_hj3jK`XI3l z_2>jdeF}+NFi#1cC2qw$C3HFQ2biaX9#7ncc}nOx#2?H2gRyuV`!V{!--+DD_ifKc(I$_Q&UV(B(Y(8)6pwj@;KA zpw!dEf%yIwY;t|uo%?lzWS?-b?E4MDx`E{-@C%=u|K=0Rl=>#I9R7$Sl=>5KBtEy| zzSZeUO(33$_9C8*b|F?ko;X^mBa47lN?k}Ci#IqC$1A1xnIs~M@k%^jsSU*0uur@I_p`(~vX63+QeWnN#yq9;zR1Pc*C)LI{S!Il zJaHCru~L^3mnijpVjboiVm;c2_wfzbcP2KX{=_EqAL6ALwrB&6@3V=QEA>_4DzqQ* z3hY}DoAG@+-p8(1>R*U!v2Gw+K}V&9^wtSUnky#&qH`Ww+`(oXxxj*p7N~w|sH5ac~G`ITViyLb$ zRV8>>a+4~-W2Z~-ar3(u{!#OjgtAxmhu%edByGH-<|h)&M?pT5kP6;PkWa>Yp^NTu)lE%}wHL2ws#$JQ zXnJQOUcAH-LoIJ=%-iS8L-(CGQRH)u7v|V!o97cj9S%bzd<=X(JNn%`&g*kJlyly~ z)1jR6GM^6RoOc4{m*bml%(MIL8#y|bb)U8Gwo`5W!et#aO_P2dPVh#Jd_F4ebMNu` z6#d4SlKN#$H6`Pwo_7kKAwU0;ydE%4f_Fd2t5@>*z>qn7(ROcc$#2zv=SqG_|5Yye zC4<)l9I{Tq3kD7$nd?0+`Te^u$jL9|zE~%}l>0)S{8H|VeDX;JfpLh3l5_~I)8$@8VBcU9Zfn0B;%I81V8+!7|$|S}YK)7M%h#=3Kr1BYV_co|} zg6-bdlwZ($+f#l)?_E*(1-&;-qH;CK3|n!vD;LAG4Qgb8uQ$mnRM$HxaD`m zWgcJCcL)jn>b`t3TojvEpp|!E2McHY?zQ|fp`GD}VJE*#Xs7Hj?BtgT?F>5%JHv42 zeAve(?9E`iC^(vNAAcJ5SL}hUYJISX=V?Rg&jjRDLsE!A5c1{tdqsO#xq%SE_L8a) zMs^MMT~S7T#zVOb{`f0T{NI4>4t?x`EtcDut-Tb4TzjQ!jU4S^`zx^b4$e^&)MGd7 z@%NGTu=d_S0g3~^{lTDLY@O-D%IyQ?`W?A8^h5?Z#eEU+&RXA&;vKuF7vp^1OZ@rNV>e~m()GzYnZiJj$-|3EDZ07}jzh>+OezP#fHn)fM z`xVb`5scF>w)FI2<(7JWXFGnetrz&6(7uY+? z*bDMfhz`K`D8s|rJI%AV$%zl!eu2FU;S{1lUW#Ea$pSg7y_rTX@Y@HSiGH!Arw=PP z4RUThHamW?jTiWR2?N#jn}xjrVvAtyJ!j+szg6P*XpyyY{7lF7+vfN^M(i=(vrRpM z`c8&D_ZQdJUb&GA{MHqk`er@9rI2&|Zgcz|=lH$ft8WwR4HR1h>vxk^-&XN^yvSNP ze#Yhc-RbzHUCOb($C`Qs_1y$}?l0J_y(5fVP~WW>;M6}6e>|*Q56HQGpId9>*iTOq zIqI$U>bnE>a<%VDufF@l@5ywE!}{fCey-nLj^Du|N52$u`_)^pmt}z**4_sYMsZNz z3@&8UAL7ZqheFryZpZH_kflB9@wYOr-y+x>D7FaJ?{u%e{0=bnhl;F~<7c3*-+gPt zJeP_+>V4?d_e|J(Ol%RXy}v@vwf7e6Re;ZSD-$`|+imOxdHG1QpM>>8_7diU97k{qb1+d5dX%B1fHWWZE@Vid@o+*M>?pDyQ z-wMYse~(8w`u!>XT)(ZbmqnR9tUY|Z81cJJ{GKC%R&G0J*Y9}8Zv}YPFMsRj`rQe8 zcFq7R$lr1!7u5GH@jIGAIIQ1gICuR{cl=h09P4{D#UOMlSF>Tl|g}K`Y1aVz_?iIesTVmU8sV z-|o2eotMWif9nIe!0#>McarC~9&-3!RY>__$M0m6S-;2Q-1U1q>~Vc#4_gm>BpC7A zCVr=ipq0Z%ni0PZj^AnES-;0%9pd`k276htMX>g`UUBQYTl}6YvR1ALa&CQBI(|7< zSifKP`qe(z%hkTqyna>O)3nnp&+jC!Uo|^^&vX2)#tnp9-~O$5Pkz>C<5eja63t-RAk*>Y|MlQ(9Ch>a_g>YEEeQ@H|W0T`|uE^2vOs_pQ z!yfZy4{L9lm*>r}$MrR@tJOft(cVC>-FQR6a?0?q_V`^7H@=-teDg()dV{cTb@P&e zy?Ppw!`d4NIoIBEj=dVl+W7ceIoJ#G$KQO=4`p~*dk4L7w9B!#NaUz@2b{X`HN&2r z3tW5OG;)F8UE;TvLO877Z$J+J2lLf#$L|u6qu(v29>IEJH|&+6+#c56LtZ`hIri!x zZ1Zxpu@}Twh{=zBD8s|rTkY9<%dy9HvG&@$@m36bSsIeV+PlviN9E$T!IQh&8%O&c zzh8l@_4{kn|AM@n346K5(Jrr_t`xt^J-;t_{q&&Yx5@FFM6x3N0QT+|TLfF*zk7a% z;6lMXUn;Uz?gP)Sy4uKbynR*dQE!$vKKNUmT=ku3vt0hUBA;EzyC+%sCSjI7u0uip89^x$OZM~Z`r8-E&TDYe!q%B z*Y9k{Z>z{rZ;r7S_;y?<&Z-eiu7_H;NqnF7W)WguPt#y}5OFh3U9l!UA9R2q3{3daumaD$qJik?tqyByP z<6-?4K+er`^VLR<*WZ5=IqDS@M%#BX?B!}-W#oePZ4tlUrBfW%??>MCx5e>$zsS+= zf1B%h(4W`ksqY>m7x>*JejlJy9Mz51@o<9C5q-yP!j3E1Fa{m%31`<&zVCn86`PeQ@1?^AjF z{>aD$^-cCSaX&?;IIQ1CaN^c?m*e+ok)z)#ufBz_mn+Ywd-a_xexIdN9Mm}zthF<9+9mHbVvl*|Z<}1dv-9}fZ{&jZT_t|^ zdVcvEK)1eq9KZVuFd0jj91^y;`eu+-%(zDvyR{Ya{PYP^V^ok?^4h2E8_P} z&u^{gcaY=vza77Prl6bWJ+Ox@o#3$T_NI{w^1NUCz9o`Y?sdqyc`kMQ{sFR-WBac3 z=8c1S{MLK(M&YqW|4*LZCEmO-(((JYO{n9*se_`YTzg6P*&z|2GA?NxX@A!Ss@yp-dx$QeSkKb!Ozw^ZJ0nhJM zp5N(?-@iD1CwYDs!ydL8g2VQgQJ&vs@%vYiv~p*8erG#=4?@=Vt7@FM^=*N@0fE}jpz3*@oV1- zVe?WAIoIz>$1lIXWc{Ax`P~nDC<+d1?`Y4j%9?!Hw@p~NzMkJ^$8RUcZ%^-fl!3im z?VItgN5$gTzQw}&O?ua(7RPUaiah2=-0j_#L888 z_1*0F<@4QbeLuuG{txPV0QPd#_s>QysBhtM#%~`g7JJ7S2 zJP*(P#XXljtgozRZ}UC)E*N5F{`j12Yj1N`{07@91Dn5sG19}t`~+yq72)sy0?7#M A*#H0l literal 0 HcmV?d00001 diff --git a/Objects/stm32f10x_usart.d b/Objects/stm32f10x_usart.d new file mode 100644 index 0000000..018c90f --- /dev/null +++ b/Objects/stm32f10x_usart.d @@ -0,0 +1,15 @@ +./objects/stm32f10x_usart.o: \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\src\stm32f10x_usart.c \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h diff --git a/Objects/stm32f10x_usart.o b/Objects/stm32f10x_usart.o new file mode 100644 index 0000000000000000000000000000000000000000..4ac696209651512c7d107aa50d6fd1938f0f53c0 GIT binary patch literal 20008 zcmcJ03v^u7dG0=Q=8Q%oA?syq^Bf!F2nCNGwuv#6NS16%vTO-Uyb`};X)G(~#b``K z%MG#(L>Q6^7AdlGp{6B)wy-b>ZSHuAxeO3fzfj?mX;G zdDBhrDChZ;jx)Ks=zpI+-tpE%Lv+enc=|X0?{supY3w-WO*fxZjnAJ{ft0FsMamVa zD=4LH<)kK(5s`|B)JJ@&d|OFJq#Ti|fYcgzvpr6fDv?qmb^5sZFLrq1o9r6{4s9q*iO^zH1q%i{0dwU(o3kFbjo zcBkW0kz*13Wi%6asi>+-{P6Vg`1FE>Elr67g}YkS;rD)hqF}1RdBFyS{3#!RPU7~W9XxAxfGUT2kMjRjc+SUuk^^9 ztIPaY=N$9-PH8^BN%*Ia>rvTLY>n}r!)i($=y>bw&iHn9KqV(9)Pe8e7vG}}7B9Sd zk2)~9$2mN@&dkZa!&nEH5jBN%uphe99Vbsa@dnK3f%s(GWNFiW{QhpzX;PR6@*|iB zS1kDR>ibm5IQ+EW=le8Xe3`w6ovF{Aa!VgP<*HiDw{u|fu7;$PQw(c9k~8w<9uLpF$mT zmDgwX=ZRAh#O5R)JmsjB=+ie(MUv>t{?ew&y|H74ngW&IFEbVx;r&UhlK5VX3N+); zjPErgkQ+Dpkulmnxkv0`)lcp@Q}&E8J`qvD80-3(vH12GOA@j8_GgPF-+p|51F}+l zFXs^Yx<0dgSXCo$ZsYh&n5dZ(^xB!8nAALL?)^1|HFCm1{4=j5_`LhbSK|9*^zLqW zJ(7&?GuCtC$CxRbJaJm(q%qdB$XaW3e*?y3Qul9CkI!s#nXgl7>9Bt0nBcoJ z9oB!R4zHgEGq)pe{@F$RvK7v)^y?us80J zx}Q-hlso0>OypuecP6pJG$4;nGh4XRrjM@j`{*k6(N!kXu#e2oPn?RCs^k-=q6#yE zsAGBg@4-_AXpf>jTFRW~%S12+$kY=iQ`44H=3HD-;khNH^Uf_PbFP`ER3z%ORumPj zD!Rf`%B@mv$$8kdqKi?vs;H<)DQ}Kytxzgqn5(1sIa?kF>Fz0x+*|p-T-I(NOY=8_<81i``A>p>spdaPKB%f6Qu@i? z6kx$b?p=HXX3u?!ra>jQ+thgjq`o4&`QxO%DpciuQcnw|zCh}kZY%~>!Z51vbGAIs z25cQukz8&rR zIV<)>T7Mz+U(V^jZ1ml~qW;UyCxh|x73!&QGN*9TC`7(Ng_GK$J)CQ(;6;Mr^dd50 z{&0Gc+;I9HwoqYFPGONzi2N-*EQ)YAZ4aNJ!it>23ZvkASYdgXuRDD=6*_VX9Y!JY zGkWOoJ(NLKm1>29RM@VY(GR7U#dfXa$5F1O9;ehO&H56fmc$}0@hl}Ka*ijAWA_(y zJP`?x_7A9Ve@@~4K;a!K+;1uPi}&YLcr>T*XrQ1Mz@ye!_zG`R;Yd#5NWQ|6GZc!M z3|`79yp*r-(isX#D!iLhcsF0+-7^$EMukc@STU7u-ioPo!z*S373y*dbw(i)i)l`H z#cZWQb55bzDEKR;+4rCqK(n5>K`IQmKSeSM!WuA2k-79T;L-~&WG6}TMlI|wkHy-? z-L!Eq=k#E{{z0v;w9~^{;fqvw)_ucw>gSecjgp^Ro;6O3tLgMxF4G;8iOwDY8P%yK zAYC2dbK0^Wq2J4|(P1o#9{Ra87L|dI=|mQbN)MyjS=^8j?aU`ttO>DCzz|Y|u0P?| zz2Bl6i2|g~b;$hD_2s3}x{6Ul*yk%+x;-t!Om$Ein~af>9Vj1MXl@^EY53 zH(Hh|9~3t=7H&=~yeL_?v#|K@r<7XclK~nz({5-cI2PtD7G@?EBWKXa|1J#6H~Z$) zVnMD{7Sqmp)5y^1$Z&c%yDHh38A_5I7))o9J4Z6fHA6eneSPV^I$7t?5?{^6Dv{o<(t#3!vlt}s$JR4?%u4`&@?#Gdt;bBQ);MB47YYS zjSTM`=r?{gG&Tjiu5`AsuP>7x8x!tzJvXMW8O>AJltCwzqCvok{oH*qqL$ zd$aB7;r{HdJVglDo`(Cle8i6!wOYE;!+qMGNFcOzyL&Qy-2+4ETvI1v#qvvMOw$ln zPZPu}Po`;OW7GOvb4$t{v>@@5=UMcaJHn>Q8UeV7e#6RtX&9t=%FVR4mcf?oJE{;zA_8%D8B9 z>iy}KhSfd0`!@At%_vD4>y|<{Ae6kZ{oy8_yZ_$m-P5BBr4<=qS zq;k#V4V;ce`qM=8l~FaGnNe|z>l57Z;WqDf0{i>tF^m_rQ1I3du{Djy7wHg zf$ZqW82%3RjNK^4n>RFWO5Y^JOqZbvVulM%SyxW@G6`QJT&LDNuWfH!r*>dH_$w7P zM)rHzF&Z1N_4K5Bb_^)zGVVh4soKkx*Nfzv9$z}NOvMrf8{(=kQlju)BvKiftL8cL zodwQ0&IPeW&JqVNU{vF#4a(sYXDRk+?xCkqqIh57+*(q67HG4-qN*RNSC_;;?|e40 zx+Iy;<31noR_69&>T&O1T@nrUXtwb_V0B4xUK{TT!gAcNVK+~X_X?{^=I6EXz9B5f zz5Ii;&E#Vy-I?S#K4Bjm$8bM*UlMMc$;V7>Gx_~}w|!8*yzdG3m-j~DHr^+N=g8MB zRzE4keWrRED+XUI-zzzbz}rMN{GRTET8DcFcO%>8-{|~T-evul*&Z0~RVuiJOYPz? z$?f50eS5f>H-+17Ua=V$Gk;C(jT_f(-Z3z|IhEQBZ4LzP0kOYjp&hY|1^0t^6bU>? z<1S2*)tKq+g)*8{)Kz=|geRvxj^h<1J{5b&{m;+r^t_lm>FnL-x$C{+8nnIbw|&lT zJK?w8XScoKw>=}$<6>SAE_aU}<>tpV*&!jvjR^LnmIoBUZ1LyFcRvCCL=V;jAK^|6P%g=k|CE(|TK)73b6u{Q7g z*d0)5^J-FFW6HZU<$WaORkmr#^Xq5goE2;L&V$X1_IimnZytiKh2@W>yd`bk+%_+c z2HLHN-R@NbYya9?+2$3~V!u~W=Y14yb${($uG`Ly-DzUQ@YaOJb~@sCZlc{=9NVem zSprq|V6pUMkzi8VYe3In<_VZ7PV93F(J@H)6Yz+aLcL25?H)Y^ir{ zFex+GdqKi7;am(QhGnn{^bBf0fm%W0vxwEhswmS+SY7qH3i(5!-tTi6_CI5SQr<`P z;_?cX$M(Y2fLT)uFxD5rU~$ST(u=3fD{RAL*LWA86>Fg&#iRYkIiACfA%Y3a1ml+EE32VI! zEjKag&4HJ4EDjfXSoM(X57|GdB|j^YxT0s3yd(PI#`Mo1?86N3JAz6^P6Z{XhCXakb`Iof(2Ve8=en|QIV;^q*pMv}coB!uOq~%{hz6AR~ zK?fHAa%#L5*Imk+oAN5!uobv>-?9@k>;499E_Rg3Tafc(?t35;%-3hEhJyu;7spa% zE~UM5YrS(=P0g~lo`t;Gh^i%BbV#~bVA2G(p1ClBynO+Z1k-+yB<5gA%|kTEB}@Q1 zS%li=)QN=q==fgb4{UG=n6ONp1*>z}r4;soevb+IV%__P$8oX8+@EnzMDHIO*S&v@ z7MN45>(;KMAOh1ZiwZltd>#+mvq?dD1oncsbdyrqEcsFQDRQ;M?FoS~c(&`f4 z00ss3BUW)$L5R;MmRxc1O)pZ3OA%0DciJGhGL;U&>e?^GDBE(-A;^P6+Dz3UB#J|Gg(*IQ<{#7A2*X5X~xvDM1Zwv7^g!mgm{LT=+GsN!-@w-C&YeW2NL;M>;e0~PW z6<2M}5vaLpTZrxn(diJ~ubxEE0jkH)SFb6LU~5S zCcaxJj})mrLi4>sIbL~ig^|xItvphu8t~{snkyGCL)16$2t)clP0v$*DSW<1D36?@ zJ`X1Od@e4JoUiziHb*DbcMvaW-`+*)_B{R)wKdP*C2BjrjX<973(6yxs#QX>FXfRM zb-C!5Yr0;o5c|IW73vt2bN*MV|H$)yg}N=z-&JZTkKd^NEsx)<&d#IPsaNviZ&TmT z<8M$6;=ftP*Qp$_zgW{eYVh?ERrK<7X^P0>-$Z5>A~OWBS8!DDzX|Rad_eFK!KVbj zCHQ^87X@DvJSoVHo_>n49*7GBYXv_hxLUAPuv>7u;7vr#_a6y;hv2ep zLi6kd{r!#L_lQ`R|3~N_3;wI%dx8mEcX}KJs|0z5fbGphtm}IABBSC)2j$rYf5c)mA1m=Qq%p>CZSt#_Sf>#K(5OG~?5_*f^ zpx`Y;TyOh?{=DFWg3Q;E3zT|V=4zu;dAJ|p;T!M_*$k>KlsNP{|mVfkr9v(8&O zpQ90%tj;^!f|!4B>F9jJEr)q0Nkm@364h8mgff( z7g~=G=2eda>`k$~7$;nXultMnd|K$Q6HArS@k3t6k9pN`f<8umCGxV!zeU8n^6W9= zjS~_4e4)=HVqPy5TJOu~6z}&a-%P~3>irn>^`w(Z-|vw>NE-8ctH@6f7o#6S-%rH6 zJ|gsE#44q}F7&fR%UhYlk8&r`wd_faDH`w+glv7ai{m)^0ve_PLv9hvmaDur*w zS(WM?8RGdLmCB?CQ}~3GN{-P!b*KOz2%WpHAQ zEj~4t&AiWS!D8-U0?%n65dSa;kAK)!2Znc!sMPRCHl13x@tUPLr+{-N?-!~$I5fLV z-m#|H#op&g)9gyY`KtF3$sHY|!0Eqgb;`zP}wgi#EG@5RW-E zHoGX!?YzG;b1-an6K5Pe3xDeFRViFf*`6K1TZS~wng{K(bhEqU`8s`Q2nqLt6+VYx zs|iXKayHM?nu6^~7arPS9ovL1NcDLI+mbF{!{4ynQQ;Ac+*eS?)}R{jV>yJqr4u-S zALF4Mwh;9N{9tc%FOY@z6Kppz8+-Sn&9-*}_9#bt?2fVbuc+Jc@%;eb^_gPq{Spnf zy;GJwY<+>fzegSFL4153r(epj7<+$*x@}J_&Be!d6W_I{+wqOUUKQF*G4|TgVEdgG zzvc^sk!yjR?Kf`uEe6l{{UhIAFu#XjkK48>#@JD=9s7%05?zek5GdPkspXez z$@s;v=Joeg*u(8gP>j7rzFaWQTmbZIzL*#}+}h;%op1TYZBpQu_f_^d$6=4Lm}2bJ z`f`Ea<>D8&TDllHzGtxeo3#ASg(T$|?^n@3+wYaIcb~T8|1tLd!j}vD9u>dl3y+ce z669>ZRhD1e{sn#?fr9P#McA{iVPo&0FBkYN2Fb{iVy!gc}zb?iv^N#Je)AIWfNK%e|uSdo9`vT~h`n%DW3;KHsH1#jRj|HSI zZK&9Ouebc-F(mN&2_$vfFOxjiyD7$Ar!N=yoe!FRO^ima9qqQ??Ur9u1Ha3CdqJK| zg2rQ5P>j85UoP-l3z~k-7fK_y1nsupU6x-wUIl)ah31#<37OAKG4?JA%`f{!zx5($ z8DuG^;|;B6zK>iawg`c}(0bMXg!Zxe(~5C_8KO%l{8>5Ty%jbN1oF^>5ms@^+73%NfuxHi^4H|nt4fXd$@oT;S8@ZQ5 z{hhS@UTOK|duO}9$7b<6;>!j7EyfKQ$N4G-hhqHRh>G3cDa$WjUj*aaAL?%m%?7N*doA;E`0BY ze?fn{#V?-)Sd84I5VHLqvHV^wa*UVXt8BlUVQ(=FNip_*9UA8e@oP>n7`cB7jq~>` zzumA&Ir`n<_am6!N!U9qJ_*Ji-(%um(BG9%ratfcS&SUtd)oayYWclRTj)@c#n{EU?P} literal 0 HcmV?d00001 diff --git a/Objects/system_stm32f10x.d b/Objects/system_stm32f10x.d new file mode 100644 index 0000000..07b4a65 --- /dev/null +++ b/Objects/system_stm32f10x.d @@ -0,0 +1,14 @@ +./objects/system_stm32f10x.o: RTE\Device\STM32F103C8\system_stm32f10x.c \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h \ + RTE\_Target_1\RTE_Components.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h \ + RTE\Device\STM32F103C8\stm32f10x_conf.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_flash.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_i2c.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_spi.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_tim.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_usart.h \ + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\misc.h diff --git a/Objects/system_stm32f10x.o b/Objects/system_stm32f10x.o new file mode 100644 index 0000000000000000000000000000000000000000..9c079a1e109afac4f06765364fd90ee8aef7c3ab GIT binary patch literal 7028 zcmb_gdvF`Y9p1gYlN3wV$#Fs)2tf`3TplOc4iM6iNS5u`#!ignq!Tb>%eEYQkSvcR zgJ}a8hwv&7C%hbnhDRxV&=~^5qcG5>g_(9*2Esr~$+R@n!nlPg4VmElL5utSPP_Km z4Kw`FP4>S1ey{!Q-tOMYH#W33a?Y75oK>+o#@OmpY>lzThAOrS+Og-O$C&o|F-;2$ zM2>P6=#C!KIXL$WuruG9o)HxhPj_Ho%k)hCt?B9Bibwz~czi4v==K1=WFB~UY>zF+ z&j6b_@#W0sY0u?v9%FpVQP%D09(%Qz5#=)WJn4%P;x`{)K{26C@Co$G&@W>H?5K~4 z2{FkgBG1fBu}Qtke~8diwdByYBN4E;}2akOlJ)TU~dPK$J1N``KnYIUUkB^1< zgtku$vQPFz(C1|LOEXj2WMrC^9Xxg^Z;Gkdp6<$7e>N~CSe5VhUuEe%qD>-~O5`#x z!pzjn)S{DQJ2Ry+V*>}D<%`fK!+2Pv6Jvg8HiLmf5l^>%V0hEq+^M-jZ}JUAFe1!2 zA~H31$5~jz-0`rOK*sx6kWXBKQHsd}pFi4N@e2+?oV-gbJ@CrR|wmiNwP~?9HI&wccHatJ~ zF)UdA?#$HZG(&QP!K1>_k8|#5m3XQ+R>tuuc4TI1{#>!gTlC`0F~&8ayWE~dyo{ga zFE@lguMVK{^s(H%h!3o>D4M26Q{7|a^WY+n7$g?4PGyr2ItM?jJYbI zz8KtnHX4k1F0^408G5}NpeWH{==CCi!I-xS@)agyKGU`n z02-qhq0FIy&ti*}@x`u4MKQ&5mTz3nSou7maSlXFEDUzm4kEH!x`t^*M}u-dWuXn` z>pudcw&zW^PYxfem$NveW)rAQ;&CxG9y8#8S*ye2c~l8OB3=2am(3e1rZ53HhSG61Yo9!G)=Lr_o^Ee-mZCCjg}f@YsO#L|pe* ziS@b(4O>fs4LUQ0A{%wx^e7V1J*H2QsO~eDDpIEh%$177^d;t5iqz{B<^_s0=qt<% z6=~Fi<~l_-VVQVnHhgsum2Sr452*V6JfLg(PHwh<-GqZpzkxHe9fWe#Z{)hURgp37 zF|SbMChjx46&dFNvrmy-e2F;#atlSfnOB$@rP<9_n|VcU;Z^3SBDeDM&FdApjfc%~ zMQ-P7%-a;XgReF3QsldQy}1`;FZFXLkC^*F>>=F6o6JWQxtq6|KLpuNX7})R^J$Qu z5SifJ=8GUN5ZS{E<}X3)VejR)nZE}46>09}cb2`aH1~0)F*g|*v_9;$;$sGNYqvE= zTX(b#X3*^0HqQ1{OuP@@PZ5xB)c*o-Yrc;lDg6wOAgXv&_*aX&gn2^dAnp;&{6dil zfu#jAN=fVy9@C@9UV#m*%+7`5$rTW|>p9_LF)vI-sXs~SjB&6jF>d{8!|nq zzP?mn@FJ_GHrSEPrq>0NxlC_5IkY2q<%Rv#;o5LGd=-m#G=%C?*9`WiLWz#H+L}fv zVrx6|*X0YTOjo{;sjY$SsMX72>pHjQQ@MQSj?wF~`Of-m???uH=Q|S}wPAAWY#2>u zhSMpQu$^PsTq>5%_Fm0KhVp|uhLFqPP=Sr$QCrhhV9}Vew~)QxLeb&j`eY#)YR&d0 z(;@8lPU`+3)L>d|-O*m-@QlFkhiqTcSA;y2z@w z!m>?!Iiw;nnM$XfN+%`IbuGr%x)c*&`*-b^iA=qjY+y8|P90^Z@=@RmGglujGogYO%qyA7Wx_pCRB@LERc z34?pXnuf`q^LSivLzD=g1>Kefx@RSqq%2ja9A|k|F?PmaEM;-?iUZ zj-akbT;eHsm%GFV@GgZq?7A5y`;F5qW0C6-;~Uk+IW`jyU;i>3@G(RN)y0ngxzjRM zy2PXyH_n9X8n__neq}`aJww=AgJjQpSUeUgk0i2!~^{o zsJjj7yGQ$tfJ=Pt9^bvoFsBFG#Hr&q(+e}u`Qd9ZP2x$|*?_$l%-b9-U?W8hoF-wv$3Y}$TTDhHH2`N#|rHcr#L{7`O_`y>H z9>T?l4&gAcQSuha@0NV8J|V?r#Zk_)|Go zUWCpqfgQN!!(E@yk1a2KbH7{#MdO!cq!hWC4MaNghcvTNBS~}^vj3%c@j5Cq+cc^?~zFBocK;)fDHllY}Xx3W;Y)tdY1;VyndM68k0QCB7r^u*8ogo{*^H zfTw=SB(9Wrp2W2h8zjahc1g?-BG$E%-$00UdYj}Egjg>RN&W+g&q;hu;vqt;r^Awe zB=NXJye_*R+8WfKeO{m+d))zP|4=_zGB)B*7k0cA5^av{ZgcpDNe;e-5dKY)w-O>w zr{vv)$SXnb1%A5;VgDE*?8YG@J+t~!JtI51l07}S)HTe)wWz?X-fV{M<;=>Z(iT3* zR%&#xZ`4*=jys^OCJ(1@HQdN0St#TNdqxVWd@)S1pB#QWkfg}+g`874IMkm#d7pDv z$)dj4sZ)w8XHupy_p8Ag$`(@Arp;R~$QN+aIeF~)zcl3Kb>YxvV>-#l^xT6p}s6%3qhU@nmy8H&Xj5jraC7%Q)UQmf~zlW1+nOnJTJD zUleN7xk!c9m$S&DokbyBXh+`+Rg~SO5G+ECNX2tl=va2F5|#2HJL0QQ5pQ@LNabNv zlB=9myp@nS)y+ipOMiWG_S@;` z7ekuu_cv(6boRab5KqN`c(%R0*sp!RAb9|G6h{?`L4{DYi3eeKrbD2bw=A%Wp;PYY zSlQ9~bdIAB;~3D2?_()+gL{&a$vU&)ss3D8erNEu>-oTwA0$C+0-QHBZYtbg3 zFe;Ta;yr|ZRUsW!%E4*p!UAYeMp8%m4`f@ZE>jCd3dn}aR#Z&cuubqFyLLr@%B~d+ z)h6}BuuD7a)KoUX$T?mg&Y=kGDpBb+s>Zv1K|BvWlvf}TRa9T}M=xi*R>TX!s1o%I bR2A>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/STM32F103C8/RTE_Device.h.base@1.1.2 b/RTE/Device/STM32F103C8/RTE_Device.h.base@1.1.2 new file mode 100644 index 0000000..0d10ed8 --- /dev/null +++ b/RTE/Device/STM32F103C8/RTE_Device.h.base@1.1.2 @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf b/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf.base@1.0.0 b/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf.base@1.0.0 new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf.base@1.0.0 @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/RTE/Device/STM32F103C8/startup_stm32f10x_md.s b/RTE/Device/STM32F103C8/startup_stm32f10x_md.s new file mode 100644 index 0000000..1ab7096 --- /dev/null +++ b/RTE/Device/STM32F103C8/startup_stm32f10x_md.s @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/RTE/Device/STM32F103C8/startup_stm32f10x_md.s.base@1.0.1 b/RTE/Device/STM32F103C8/startup_stm32f10x_md.s.base@1.0.1 new file mode 100644 index 0000000..1ab7096 --- /dev/null +++ b/RTE/Device/STM32F103C8/startup_stm32f10x_md.s.base@1.0.1 @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/RTE/Device/STM32F103C8/stm32f10x_conf.h b/RTE/Device/STM32F103C8/stm32f10x_conf.h new file mode 100644 index 0000000..228bd40 --- /dev/null +++ b/RTE/Device/STM32F103C8/stm32f10x_conf.h @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.6.0 + * @date 20-September-2021 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Run Time Environment will set specific #define for each selected module below */ +#include "RTE_Components.h" + +#ifdef RTE_DEVICE_STDPERIPH_ADC +#include "stm32f10x_adc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_BKP +#include "stm32f10x_bkp.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CAN +#include "stm32f10x_can.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CEC +#include "stm32f10x_cec.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CRC +#include "stm32f10x_crc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DAC +#include "stm32f10x_dac.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DBGMCU +#include "stm32f10x_dbgmcu.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DMA +#include "stm32f10x_dma.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_EXTI +#include "stm32f10x_exti.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FLASH +#include "stm32f10x_flash.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FSMC +#include "stm32f10x_fsmc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_GPIO +#include "stm32f10x_gpio.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_I2C +#include "stm32f10x_i2c.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_IWDG +#include "stm32f10x_iwdg.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_PWR +#include "stm32f10x_pwr.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_RCC +#include "stm32f10x_rcc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_RTC +#include "stm32f10x_rtc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_SDIO +#include "stm32f10x_sdio.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_SPI +#include "stm32f10x_spi.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_TIM +#include "stm32f10x_tim.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_USART +#include "stm32f10x_usart.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_WWDG +#include "stm32f10x_wwdg.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ diff --git a/RTE/Device/STM32F103C8/stm32f10x_conf.h.base@3.6.0 b/RTE/Device/STM32F103C8/stm32f10x_conf.h.base@3.6.0 new file mode 100644 index 0000000..228bd40 --- /dev/null +++ b/RTE/Device/STM32F103C8/stm32f10x_conf.h.base@3.6.0 @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.6.0 + * @date 20-September-2021 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Run Time Environment will set specific #define for each selected module below */ +#include "RTE_Components.h" + +#ifdef RTE_DEVICE_STDPERIPH_ADC +#include "stm32f10x_adc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_BKP +#include "stm32f10x_bkp.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CAN +#include "stm32f10x_can.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CEC +#include "stm32f10x_cec.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CRC +#include "stm32f10x_crc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DAC +#include "stm32f10x_dac.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DBGMCU +#include "stm32f10x_dbgmcu.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DMA +#include "stm32f10x_dma.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_EXTI +#include "stm32f10x_exti.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FLASH +#include "stm32f10x_flash.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FSMC +#include "stm32f10x_fsmc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_GPIO +#include "stm32f10x_gpio.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_I2C +#include "stm32f10x_i2c.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_IWDG +#include "stm32f10x_iwdg.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_PWR +#include "stm32f10x_pwr.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_RCC +#include "stm32f10x_rcc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_RTC +#include "stm32f10x_rtc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_SDIO +#include "stm32f10x_sdio.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_SPI +#include "stm32f10x_spi.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_TIM +#include "stm32f10x_tim.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_USART +#include "stm32f10x_usart.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_WWDG +#include "stm32f10x_wwdg.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ diff --git a/RTE/Device/STM32F103C8/system_stm32f10x.c b/RTE/Device/STM32F103C8/system_stm32f10x.c new file mode 100644 index 0000000..9e31f67 --- /dev/null +++ b/RTE/Device/STM32F103C8/system_stm32f10x.c @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/RTE/Device/STM32F103C8/system_stm32f10x.c.base@1.0.1 b/RTE/Device/STM32F103C8/system_stm32f10x.c.base@1.0.1 new file mode 100644 index 0000000..9e31f67 --- /dev/null +++ b/RTE/Device/STM32F103C8/system_stm32f10x.c.base@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/RTE/_Target_1/RTE_Components.h b/RTE/_Target_1/RTE_Components.h new file mode 100644 index 0000000..7bd409b --- /dev/null +++ b/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,36 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'example' + * Target: 'Target_1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + +/* Keil::Device:StdPeriph Drivers:Flash@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_FLASH +/* Keil::Device:StdPeriph Drivers:Framework@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_FRAMEWORK +/* Keil::Device:StdPeriph Drivers:GPIO@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_GPIO +/* Keil::Device:StdPeriph Drivers:I2C@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_I2C +/* Keil::Device:StdPeriph Drivers:RCC@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_RCC +/* Keil::Device:StdPeriph Drivers:SPI@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_SPI +/* Keil::Device:StdPeriph Drivers:TIM@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_TIM +/* Keil::Device:StdPeriph Drivers:USART@3.6.0 */ +#define RTE_DEVICE_STDPERIPH_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/example.uvguix.gxyos b/example.uvguix.gxyos new file mode 100644 index 0000000..6556f64 --- /dev/null +++ b/example.uvguix.gxyos @@ -0,0 +1,3746 @@ + + + + -6.1 + +
    ### uVision Project, (C) Keil Software
    + + + C:\Users\gxyos\Documents\ST30F103\Example\DEV + + + + + System Viewer\GPIOB + 35903 + + 109 + + + System Viewer\GPIOC + 35904 + + 109 + + + System Viewer\RCC + 35905 + + 80 + + + + + + 38003 + Registers + 218 218 + + + 346 + Code Coverage + 1010 160 + + + 204 + Performance Analyzer + 1170 + + + + + + 35141 + Event Statistics + + 200 50 700 + + + 1506 + Symbols + + 80 80 80 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 300 + + + + + + + + 0 + 0 + 0 + 50 + 16 + + + + + + + 44 + 2 + 3 + + -32000 + -32000 + + + -1 + -1 + + + 287 + 147 + 960 + 957 + + + + 0 + + 1692 + 0100000004000000010000000100000001000000010000000000000002000000000000000100000001000000000000002800000028000000010000000D000000080000000100000034433A5C55736572735C6778796F735C446F63756D656E74735C53543330463130335C4578616D706C655C4150505C6D61696E2E6300000000066D61696E2E6300000000C5D4F200FFFFFFFF6B433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C4B65696C5C53544D3332463178785F4446505C322E342E315C4465766963655C5374645065726970685F4472697665725C7372635C73746D3332663130785F7263632E63000000000F73746D3332663130785F7263632E6300000000FFDC7800FFFFFFFF6B433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C4B65696C5C53544D3332463178785F4446505C322E342E315C4465766963655C5374645065726970685F4472697665725C696E635C73746D3332663130785F7263632E68000000000F73746D3332663130785F7263632E6800000000BECEA100FFFFFFFF5A433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C4B65696C5C53544D3332463178785F4446505C322E342E315C4465766963655C496E636C7564655C73746D3332663130782E68000000000B73746D3332663130782E6800000000F0A0A100FFFFFFFF57433A5C55736572735C6778796F735C446F63756D656E74735C53543330463130335C4578616D706C655C5254455C4465766963655C53544D33324631303343385C737461727475705F73746D3332663130785F6D642E730000000016737461727475705F73746D3332663130785F6D642E7300000000BCA8E100FFFFFFFF6C433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C4B65696C5C53544D3332463178785F4446505C322E342E315C4465766963655C5374645065726970685F4472697665725C7372635C73746D3332663130785F6770696F2E63000000001073746D3332663130785F6770696F2E63000000009CC1B600FFFFFFFF6C433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C4B65696C5C53544D3332463178785F4446505C322E342E315C4465766963655C5374645065726970685F4472697665725C696E635C73746D3332663130785F6770696F2E68000000001073746D3332663130785F6770696F2E6800000000F7B88600FFFFFFFF53433A5C55736572735C6778796F735C446F63756D656E74735C53543330463130335C4578616D706C655C5254455C4465766963655C53544D33324631303343385C73797374656D5F73746D3332663130782E63000000001273797374656D5F73746D3332663130782E6300000000D9ADC200FFFFFFFF33433A5C55736572735C6778796F735C446F63756D656E74735C53543330463130335C4578616D706C655C4445565C6969632E6300000000056969632E6300000000A5C2D700FFFFFFFF33433A5C55736572735C6778796F735C446F63756D656E74735C53543330463130335C4578616D706C655C4445565C6969632E6800000000056969632E6800000000B3A6BE00FFFFFFFF62433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C4B65696C5C53544D3332463178785F4446505C322E342E315C4465766963655C5374645065726970685F4472697665725C7372635C6D6973632E6300000000066D6973632E6300000000EAD6A300FFFFFFFF61433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C4B65696C5C53544D3332463178785F4446505C322E342E315C4465766963655C496E636C7564655C73797374656D5F73746D3332663130782E68000000001273797374656D5F73746D3332663130782E6800000000F6FA7D00FFFFFFFF54433A5C55736572735C6778796F735C417070446174615C4C6F63616C5C41726D5C5061636B735C41524D5C434D5349535C362E312E305C434D5349535C436F72655C496E636C7564655C636F72655F636D332E68000000000A636F72655F636D332E6800000000B5E99D00FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000C20100006600000080070000AF020000 + + + + 0 + Build + + -1 + -1 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F40000004F00000090050000DD000000 + + + 16 + F40000006600000090050000F4000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BB0100007F020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 109 + 109 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BB0100007F020000 + + + 16 + F2000000090100000E02000045030000 + + + + 1465 + 1465 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 1935 + 1935 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 195 + 195 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BB0100007F020000 + + + 16 + F2000000090100000E02000045030000 + + + + 196 + 196 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BB0100007F020000 + + + 16 + F2000000090100000E02000045030000 + + + + 197 + 197 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 00000000B002000080070000DE030000 + + + 16 + F200000009010000BA03000097010000 + + + + 198 + 198 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000001502000090050000B7020000 + + + 16 + F200000009010000BA03000097010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30200007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 203 + 203 + 0 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 38003 + 38003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BB0100007F020000 + + + 16 + F2000000090100000E02000045030000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30200007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30200007D070000C5030000 + + + 16 + F2000000090100000E02000045030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30200007D070000C5030000 + + + 16 + F2000000090100000E02000045030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30200007D070000C5030000 + + + 16 + F2000000090100000E02000045030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D0500000C020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000DE03000080070000F1030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 1 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 0 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 00000000380000006F02000054000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000002C0200008D0500009E020000 + + + 16 + F200000009010000E2010000D2010000 + + + + 3312 + 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFF4000000DD00000090050000E1000000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000F40000006600000090050000F4000000F40000004F00000090050000DD0000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF9C0400004F000000A004000025020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000A004000066000000900500003C020000A00400004F000000900500002502000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFBE0100004F000000C20100009802000001000000020000100400000001000000C4FEFFFF39060000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000BE010000AF020000000000004F000000BE010000980200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF0000000011020000900500001502000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000000000000000000002C02000090050000CE020000000000001502000090050000B702000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFC802000015020000CC020000B702000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF0000000098020000800700009C0200000100000001000010040000000100000008FDFFFF8C000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF010000779400000180008000000100000000000000B302000080070000F5030000000000009C02000080070000DE0300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2572 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000F46756E6374696F6E616C5374617465960000000000000001000F46756E6374696F6E616C537461746500000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 976 + 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000000000000100000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA0000000000000000000000000000000000000000000000000100000001000000960000000300205000000000085461726765745F3196000000000000000100085461726765745F31000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2373 + 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1920 + 1080 + + + + 1 + Debug + + -1 + -1 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F40000004F0000002D060000DD000000 + + + 16 + F4000000660000002D060000F4000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED0000001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 109 + 109 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED0000001F030000 + + + 16 + F2000000090100000E02000045030000 + + + + 1465 + 1465 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000002A060000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 1935 + 1935 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 195 + 195 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED0000001F030000 + + + 16 + F2000000090100000E02000045030000 + + + + 196 + 196 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED0000001F030000 + + + 16 + F2000000090100000E02000045030000 + + + + 197 + 197 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000400200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 198 + 198 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000003C030000C0030000DE030000 + + + 16 + F200000009010000BA03000097010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000400200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 203 + 203 + 1 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + F4000000630000002D060000DD000000 + + + 16 + F200000009010000BA03000097010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000002A060000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000BA03000097010000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000002A060000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000002A060000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000002A060000C4000000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000002A060000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35903 + 35903 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35904 + 35904 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 35905 + 35905 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 38003 + 38003 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED0000001F030000 + + + 16 + F2000000090100000E02000045030000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000400200008D0500009E020000 + + + 16 + F200000009010000BA03000097010000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000400200008D0500009E020000 + + + 16 + F2000000090100000E02000045030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000400200008D0500009E020000 + + + 16 + F2000000090100000E02000045030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000400200008D0500009E020000 + + + 16 + F2000000090100000E02000045030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000002A060000C4000000 + + + 16 + F200000009010000BA03000097010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 34060000660000007D0700001F030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000DE03000080070000F1030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 0 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 1 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 000000001C0000006F02000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000530300007D070000C5030000 + + + 16 + F200000009010000E2010000D2010000 + + + + 3324 + 000000000B000000000000000020000001000000FFFFFFFFFFFFFFFFF4000000DD0000002D060000E1000000010000000100001004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000001000000F4000000660000002D060000F4000000F40000004F0000002D060000DD0000000000000040280056080000000B446973617373656D626C7901000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000001000000FFFFFFFFFFFFFFFF2D0600004F0000003106000038030000010000000200001004000000010000006DFAFFFFEE000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C30000018000400000010000003106000066000000800700004F030000310600004F000000800700003803000000000000404100562B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF054750494F42010000003F8C000001000000FFFFFFFFFFFFFFFF054750494F4301000000408C000001000000FFFFFFFFFFFFFFFF0352434301000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFF15000000000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFF00000004F000000F400000038030000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000F00000004F030000000000004F000000F0000000380300000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73000000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7300000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657300000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273010000007394000001000000FFFFFFFFFFFFFFFF04000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000001000000FFFFFFFFFFFFFFFF0000000038030000800700003C03000001000000010000100400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000001000000C40300005303000080070000F5030000C40300003C03000080070000DE03000000000000404100560F0000001343616C6C20537461636B202B204C6F63616C73010000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203101000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFF000000000000000001000000000000000100000001000000FFFFFFFFC00300003C030000C4030000DE03000001000000020000100400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000000000000FFFFFFFFFFFFFFFF00000000250200009005000029020000000000000100000004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000000000000000000004002000090050000CE020000000000002902000090050000B70200000000000040820046060000000C4275696C64204F757470757400000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0642726F777365000000007794000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2798 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000F46756E6374696F6E616C5374617465960000000000000013000F46756E6374696F6E616C537461746500084375745F466C61670949735F437574696E670D45585449305F44697361626C650A4750494F5F50696E5F34084375745F496E69740D534A5F57524954455F54494D450E5354373738395F57525F444154410D5354373738395F57525F5245470C4C43445F57525F44415441380A4C43445F57525F524547044932433003753136037533320275380464726177074D454D5F4D4F4E034D454D00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000300150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 955 + 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2362 + 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 8 + + .\APP\main.c + 2 + 1 + 23 + 1 + + 0 + + + C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_rcc.c + 33 + 1206 + 1237 + 1 + + 0 + + + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h + 28 + 468 + 499 + 1 + + 0 + + + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\stm32f10x.h + 14 + 1017 + 1018 + 1 + + 0 + + + RTE/Device/STM32F103C8/startup_stm32f10x_md.s + 0 + 125 + 135 + 1 + + 0 + + + C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/stm32f10x_gpio.c + 0 + 44 + 45 + 1 + + 0 + + + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\StdPeriph_Driver\inc\stm32f10x_gpio.h + 17 + 330 + 356 + 1 + + 0 + + + RTE/Device/STM32F103C8/system_stm32f10x.c + 14 + 49 + 64 + 1 + + 0 + + + .\DEV\iic.c + 2 + 400 + 447 + 0 + + 0 + + + DEV\iic.h + 12 + 1 + 5 + 0 + + 0 + + + C:/Users/gxyos/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.1/Device/StdPeriph_Driver/src/misc.c + 0 + 1 + 1 + 1 + + 0 + + + C:\Users\gxyos\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include\system_stm32f10x.h + 0 + 1 + 1 + 1 + + 0 + + + C:\Users\gxyos\AppData\Local\Arm\Packs\ARM\CMSIS\6.1.0\CMSIS\Core\Include\core_cm3.h + 0 + 1 + 1 + 1 + + 0 + + + + +     diff --git a/example.uvoptx b/example.uvoptx new file mode 100644 index 0000000..33b8dbf --- /dev/null +++ b/example.uvoptx @@ -0,0 +1,274 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Target_1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -UR -O16590 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 -WK0-R0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOB + 35903 + + + System Viewer\GPIOC + 35904 + + + System Viewer\RCC + 35905 + + + + 0 + 0 + 0 + 2 + 10000000 + + + + + + APP + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\APP\main.c + main.c + 0 + 0 + + + + + DEV + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 1 + 0 + 0 + .\DEV\iic.c + iic.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + +     diff --git a/example.uvprojx b/example.uvprojx new file mode 100644 index 0000000..3a5540f --- /dev/null +++ b/example.uvprojx @@ -0,0 +1,529 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Target_1 + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + STM32F103C8 + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)) + 0 + $$Device:STM32F103C8$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103C8$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + example + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + .\DEV + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + APP + + + main.c + 1 + .\APP\main.c + + + + + DEV + + + iic.c + 1 + .\DEV\iic.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F103C8\RTE_Device.h + + + + + + + + RTE\Device\STM32F103C8\startup_stm32f10x_md.s + + + + + + + + RTE\Device\STM32F103C8\stm32f10x_conf.h + + + + + + + + RTE\Device\STM32F103C8\system_stm32f10x.c + + + + + + + + + + + + + example + 1 + + + + +